Specifications
| Type | Description |
|---|---|
| Part Number | ADS1110A0IDBVR |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package Case | SOT23-6, package designator DBV |
| ADC Architecture | Delta-sigma analog-to-digital converter; differential switched-capacitor modulator with digital filter |
| Resolution, Maximum | 16 bits maximum; DR=11, 15 SPS mode |
| No Missing Codes | 16 bits no missing codes; maximum resolution mode |
| Input Type | Fully differential inputs; VIN+ and VIN- analog inputs |
| Full-Scale Input Voltage | ±2.048/PGA V; (VIN+) - (VIN-) |
| Full-Scale Range | 4.096/PGA V; FSR = 2 × 2.048 V / PGA |
| Analog Input Voltage Range | GND - 0.2 V to VDD + 0.2 V; VIN+ to GND or VIN- to GND |
| Differential Input Impedance | 2.8/PGA MΩ typical |
| Common-Mode Input Impedance, PGA=1 | 3.5 MΩ |
| Common-Mode Input Impedance, PGA=2 | 3.5 MΩ |
| Common-Mode Input Impedance, PGA=4 | 1.8 MΩ |
| Common-Mode Input Impedance, PGA=8 | 0.9 MΩ |
| Programmable Gain Amplifier | Gain up to 8; onboard PGA |
| PGA Gain Settings | 1, 2, 4, 8 |
| Onboard Reference Voltage | 2.048 V ±0.05%; internal reference |
| Reference Drift | 5 ppm/°C; onboard reference |
| External Reference Support | Not supported; internal 2.048 V reference always used |
| Data Rate, DR=00 | 180 min, 240 typ, 308 max SPS |
| Resolution, DR=00 | 12 bits min, 12 bits max |
| Data Rate, DR=01 | 45 min, 60 typ, 77 max SPS |
| Resolution, DR=01 | 14 bits min, 14 bits max |
| Data Rate, DR=10 | 22 min, 30 typ, 39 max SPS |
| Resolution, DR=10 | 15 bits min, 15 bits max |
| Data Rate, DR=11 | 11 min, 15 typ, 20 max SPS |
| Resolution, DR=11 | 16 bits min, 16 bits max |
| Integral Nonlinearity | ±0.004 typ, ±0.010 max % of FSR; DR=11, PGA=1, endpoint fit, 99% of full-scale |
| Offset Error, PGA=1 | 1.2 typ, 8 max mV |
| Offset Error, PGA=2 | 0.7 typ, 4 max mV |
| Offset Error, PGA=4 | 0.5 typ, 2.5 max mV |
| Offset Error, PGA=8 | 0.4 typ, 1.5 max mV |
| Offset Drift, PGA=1 | 1.2 typ µV/°C |
| Offset Drift, PGA=2 | 0.6 typ µV/°C |
| Offset Drift, PGA=4 | 0.3 typ µV/°C |
| Offset Drift, PGA=8 | 0.3 typ µV/°C |
| Offset vs VDD, PGA=1 | 800 typ µV/V |
| Offset vs VDD, PGA=2 | 400 typ µV/V |
| Offset vs VDD, PGA=4 | 200 typ µV/V |
| Offset vs VDD, PGA=8 | 150 typ µV/V |
| Gain Error | 0.05 typ, 0.40 max %; includes onboard PGA and reference errors |
| PGA Gain Error Match | 0.02 typ, 0.10 max %; match between any two PGA gains |
| Gain Error Drift | 5 typ, 40 max ppm/°C; includes onboard PGA and reference errors |
| Gain vs VDD | 80 typ ppm/V; specifications at VDD=5 V unless otherwise noted |
| Common-Mode Rejection, PGA=8 | 95 typ, 105 max dB; at DC |
| Common-Mode Rejection, PGA=1 | 100 typ dB; at DC |
| Digital Interface | I2C-compatible serial interface; eight available addresses |
| I2C Address | 1001000; ADS1110A0 variant, ordering number ADS1110A0IDBVR |
| Logic Input High Voltage | 0.7 × VDD min, 6 max V; VIH |
| Logic Input Low Voltage | GND - 0.5 min, 0.3 × VDD max V; VIL |
| Logic Output Low Voltage | GND min, 0.4 max V; VOL, IOL=3 mA |
| Input Leakage High | 10 µA; IH, VIH=5.5 V |
| Input Leakage Low | -10 µA; IL, VIL=GND |
| Power-Supply Voltage | 2.7 min, 5.5 max V; VDD |
| Supply Current, Power-Down Mode | 0.05 typ, 2 max µA |
| Supply Current, Active Mode | 240 typ, 350 max µA |
| Power Dissipation, VDD=5.0 V | 1.2 typ, 1.75 max mW |
| Power Dissipation, VDD=3.0 V | 0.675 typ mW |
| Operating Temperature Range | -40°C to +85°C; specified for ADS1110A0IDBVR |
| Absolute Maximum VDD to GND | -0.3 V to +6 V |
| Absolute Maximum Input Current, Momentary | 100 mA |
| Absolute Maximum Input Current, Continuous | 10 mA |
| Absolute Maximum Analog Pin Voltage | -0.3 V to VDD + 0.3 V; VIN+ or VIN- to GND |
| Absolute Maximum Digital Pin Voltage | -0.5 V to 6 V; SDA or SCL to GND |
| Maximum Junction Temperature | +150°C |
| Storage Temperature Range | -60°C to +150°C |
| Lead Temperature | +300°C; soldering, 10 s |
| Conversion Modes | Continuous and single-conversion modes; single-conversion mode powers down after conversion |
| Clock Source | Onboard oscillator only; external system clock operation not possible |
| Nominal Clock Frequency | 275 kHz; onboard clock oscillator |
| Output Code Format | Binary two's complement, right-justified and sign-extended |
| Output Code Range, 15 SPS | -32768 to 32767; 16-bit mode |
| Output Code Range, 30 SPS | -16384 to 16383; 15-bit mode |
| Output Code Range, 60 SPS | -8192 to 8191; 14-bit mode |
| Output Code Range, 240 SPS | -2048 to 2047; 12-bit mode |
| Ordering Number | ADS1110A0IDBVR; tape and reel, 3000 quantity |
| Package Marking | ED0; ADS1110A0 package marking |
| Datasheet Status | request_only |
Product Overview
The ADS1110A0IDBVR is a Texas Instruments Signal_Chain device described as a 16-bit delta-sigma ADC. Its architecture uses a differential switched-capacitor modulator with a digital filter, fully differential analog inputs, and binary two's complement output data that is right-justified and sign-extended.
Key Features
- 16-bit delta-sigma ADC maximum resolution
- Differential switched-capacitor modulator with digital filter
- Fully differential VIN+ and VIN- analog inputs
- Internal 2.048 V reference with 5 ppm/°C drift
- Onboard PGA supports gain settings 1, 2, 4, 8
- Data rates from 15 SPS to 240 SPS typical
- I2C-compatible serial interface with address 1001000
- Continuous and single-conversion operating modes
- Onboard oscillator with 275 kHz nominal frequency
- Power-down supply current 0.05 µA typical
Typical Applications
- Differential signal digitization
- I2C data acquisition nodes
- Low-power measurement circuits
- Single-conversion measurement systems
- Continuous monitoring inputs
- PGA-scaled sensor measurements
Procurement Notes
When requesting a quote for ADS1110A0IDBVR, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What resolution modes does ADS1110A0IDBVR support?
ADS1110A0IDBVR supports 12-bit operation at DR=00, 14-bit operation at DR=01, 15-bit operation at DR=10, and 16-bit operation at DR=11. The typical data rates are 240, 60, 30, and 15 SPS respectively.
Does ADS1110A0IDBVR use an external reference?
No. The extracted datasheet facts state that external reference support is not available. ADS1110A0IDBVR always uses its internal 2.048 V reference, specified with ±0.05% value and 5 ppm/°C reference drift.
What input range is supported by the ADC inputs?
The differential full-scale input voltage is ±2.048/PGA V, giving a full-scale range of 4.096/PGA V. The analog input voltage range for VIN+ or VIN- to GND is GND - 0.2 V to VDD + 0.2 V.
What package and interface does this part use?
ADS1110A0IDBVR is supplied in a SOT23-6 package with DBV package designator. Its digital interface is I2C-compatible, and the ADS1110A0 variant uses I2C address 1001000.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.