Specifications
| Type | Description |
|---|---|
| Part Number | ADS1258 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | RTC package, QFN-48 |
| Resolution | 24 bits, no missing codes; System performance |
| Input Channels | 16 single-ended or 8 differential inputs; Analog input multiplexer |
| Fixed-Channel Data Rate | 1.953 to 125 kSPS; Fixed-channel mode |
| Auto-Scan Data Rate | 1.805 to 23.739 kSPS; Auto-scan mode |
| Full-Scale Input Voltage | ±1.06 VREF; VIN = ADCINP - ADCINN |
| Analog Input Absolute Voltage | AVSS - 100 mV to AVDD + 100 mV; AIN0-AIN15 and AINCOM with respect to DGND |
| ADC Input Absolute Voltage | AVSS - 100 mV to AVDD + 100 mV; ADCINP, ADCINN |
| Differential Input Impedance | 65 kΩ typ; ADC input |
| On-Channel Resistance | 80 Ω typ; Analog multiplexer inputs |
| Crosstalk | -110 dB typ; fIN = 1 kHz |
| Sensor Bias Current Source | 1.5 µA typ; SBCS[1:0] = 01 |
| Sensor Bias Current Source | 24 µA typ; SBCS[1:0] = 11 |
| Sensor Bias Current Ratio Error | 1% typ; 1.5 µA : 24 µA ratio |
| Integral Nonlinearity | 0.0003% typ, 0.0010% max of FSR; Differential input, best straight-line fit; FSR = 2.13 VREF |
| Offset Error | 20 µV typ; Shorted inputs, chopping off |
| Offset Error | 1 µV typ, 10 µV max; Shorted inputs, chopping on |
| Offset Drift | 0.5 µV/°C typ; Shorted inputs, chopping off; ensured by characterization |
| Offset Drift | 0.02 µV/°C typ, 0.1 µV/°C max; Shorted inputs, chopping on; ensured by characterization |
| Gain Error | 0.1% typ, 0.5% max; System performance |
| Gain Drift | 0.4 ppm/°C typ, 2 ppm/°C max; Ensured by characterization |
| Common-Mode Rejection | 90 dB min, 100 dB typ; fCM = 60 Hz |
| Power-Supply Rejection | 70 dB min, 85 dB typ; AVDD, AVSS; fPS = 60 Hz |
| Power-Supply Rejection | 80 dB min, 95 dB typ; DVDD; fPS = 60 Hz |
| Reference Input Voltage | 0.5 V min, 4.096 V typ, AVDD - AVSS max; VREF = VREFP - VREFN |
| Negative Reference Input | AVSS - 0.1 V min, VREFP - 0.5 V max; VREFN |
| Positive Reference Input | VREFN + 0.5 V min, AVDD + 0.1 V max; VREFP |
| Reference Input Impedance | 40 kΩ typ; Voltage reference input |
| External Reference Reading Error | 1% typ, 3% max; System monitor parameter |
| Analog Supply Reading Error | 1% typ, 3% max; System monitor parameter |
| Temperature Sensor Voltage | 168 mV typ; TA = +25°C; only ADS1258 temperature forced, test PCB in free air |
| Temperature Sensor Coefficient | 394 µV/°C typ; Only ADS1258 temperature forced, test PCB in free air |
| Temperature Sensor Coefficient | 563 µV/°C typ; ADS1258 and test PCB temperatures forced together |
| Digital Input High Voltage | 0.7 DVDD min, DVDD max; VIH logic level |
| Digital Input Low Voltage | DGND min, 0.3 DVDD max; VIL logic level |
| Digital Output High Voltage | 0.8 DVDD min, DVDD max; VOH, IOH = 2 mA |
| Digital Output Low Voltage | DGND min, 0.2 DVDD max; VOL, IOL = 2 mA |
| Digital Input Leakage | 10 µA max; VIN = DVDD or GND |
| Master Clock Input Frequency | 0.1 to 16 MHz; CLKIO external clock input |
| Master Clock Input Duty Cycle | 40% to 60%; CLKIO external clock input |
| Crystal Frequency | 32.768 kHz; Crystal oscillator |
| Crystal Oscillator Clock Output Frequency | 15.729 MHz; Crystal oscillator |
| Crystal Oscillator Start-Up Time | 150 ms typ; Clock output valid |
| Clock Output Duty Cycle | 40% to 60%; Crystal oscillator clock output |
| Digital Supply Voltage | 2.7 to 5.25 V; DVDD |
| Negative Analog Supply Voltage | -2.6 to 0 V; AVSS |
| Positive Analog Supply Voltage | AVSS + 4.75 V to AVSS + 5.25 V; AVDD |
| DVDD Supply Current | 0.25 mA typ, 0.6 mA max; External clock operation |
| DVDD Supply Current | 0.04 mA typ; Internal oscillator operation, clock output disabled |
| DVDD Supply Current | 1.4 mA typ; Internal oscillator operation, clock output enabled; CLKIO load = 20 pF |
| DVDD Power-Down Supply Current | 1 µA typ, 25 µA max; Power-down; no clock applied to CLKIO |
| AVDD/AVSS Supply Current | 8.2 mA typ, 12 mA max; Converting |
| AVDD/AVSS Supply Current | 5.6 mA typ; Standby |
| AVDD/AVSS Supply Current | 2.1 mA typ; Sleep |
| AVDD/AVSS Supply Current | 2 µA typ, 85 µA max; Power-down |
| Power Dissipation | 42 mW typ, 62 mW max; Converting |
| Power Dissipation | 29 mW typ; Standby |
| Power Dissipation | 11 mW typ; Sleep |
| Power Dissipation | 14 µW typ; Power-down |
| Operating Temperature Range | -40°C to +105°C; Absolute maximum ratings table |
| Storage Temperature Range | -60°C to +150°C; Absolute maximum ratings table |
| Maximum Junction Temperature | +150°C; Absolute maximum ratings table |
| AVDD to AVSS Absolute Maximum | -0.3 to +5.5 V; Absolute maximum rating |
| AVSS to DGND Absolute Maximum | -2.8 to +0.3 V; Absolute maximum rating |
| DVDD to DGND Absolute Maximum | -0.3 to +5.5 V; Absolute maximum rating |
| Analog Input Voltage Absolute Maximum | AVSS - 0.3 V to AVDD + 0.3 V; Absolute maximum rating |
| Digital Input Voltage Absolute Maximum | -0.3 V to DVDD + 0.3 V; With respect to DGND |
| Input Current Absolute Maximum | 100 mA; Momentary |
| Input Current Absolute Maximum | 10 mA; Continuous |
| SPI SCLK Period | 2 τCLK min; Serial interface timing, TA = -40°C to +105°C, DVDD = 2.7 V to 5.25 V |
| SPI SCLK High or Low Pulse Width | 0.8 to 4096 τCLK; Exceeding max resets SPI interface; programmable to 256 τCLK |
| CS Low to First SCLK Setup Time | 2.5 τCLK min; CS can be tied low |
| DIN Setup Time | 10 ns min; Valid DIN to SCLK rising edge |
| DIN Hold Time | 5 ns min; Valid DIN to SCLK rising edge |
| DOUT Propagation Delay | 20 ns max; SCLK falling edge to valid new DOUT; DOUT load = 20 pF || 100 kΩ to DGND |
| DOUT Hold Time | 0 ns min; SCLK falling edge to old DOUT invalid |
| CS High to DOUT Invalid | 5 τCLK max; DOUT tri-state |
| CS Pulse Width High | 2 τCLK min; Serial interface timing |
| DRDY High Pulse Width | 1 τCLK typ; Without data read |
| Valid DOUT to DRDY Falling Edge | 0.5 τCLK typ; CS = 0 |
| Interface | SPI-compatible serial interface; Digital communication |
| GPIO Count | 8 general-purpose inputs/outputs; GPIO[7:0] |
| Datasheet Status | request_only |
Product Overview
The ADS1258 is a Texas Instruments Signal_Chain converter specified as a 16-channel 24-bit delta-sigma ADC. Its analog input multiplexer supports 16 single-ended or 8 differential inputs, while the converter provides 24-bit resolution with no missing codes. Conversion throughput is specified from 1.953 to 125 kSPS in fixed-channel mode and from 1.805 to 23.739 kSPS in auto-scan mode.
The device uses an RTC package, QFN-48, and supports a SPI-compatible serial interface with timing specifications for SCLK, CS, DIN, DOUT, and DRDY. It also includes 8 general-purpose inputs/outputs on GPIO[7:0]. Clocking can use an external CLKIO input from 0.1 to 16 MHz or a 32.768 kHz crystal oscillator with a 15.729 MHz clock output.
Analog performance parameters include ±1.06 VREF full-scale input voltage, 65 kΩ typical differential input impedance, 80 Ω typical on-channel resistance, -110 dB typical crosstalk at 1 kHz, and common-mode rejection of 90 dB minimum and 100 dB typical at 60 Hz. Integrated monitor functions cover external reference, analog supply, and temperature-sensor measurements for multichannel sensor and system-monitoring designs.
Key Features
- 24-bit delta-sigma ADC with no missing codes
- 16 single-ended or 8 differential analog inputs
- Fixed-channel data rate from 1.953 to 125 kSPS
- Auto-scan data rate from 1.805 to 23.739 kSPS
- SPI-compatible serial interface with defined timing parameters
- 8 general-purpose inputs and outputs on GPIO[7:0]
- Sensor bias current sources at 1.5 µA and 24 µA
- Integrated external reference, analog supply, and temperature monitoring
- 0.1 to 16 MHz external master clock input
- -40°C to +105°C operating temperature range
Typical Applications
- Multichannel sensor measurement
- Differential input data acquisition
- Single-ended analog input scanning
- SPI-connected measurement systems
- Reference and supply monitoring
- Temperature-sensor monitoring
- GPIO-assisted data acquisition
- Low-power standby and sleep systems
Procurement Notes
When requesting a quote for ADS1258, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of converter is the ADS1258?
The ADS1258 is a Texas Instruments 16-channel 24-bit delta-sigma ADC in the Signal_Chain category. The extracted specifications state 24-bit resolution with no missing codes and support for 16 single-ended or 8 differential analog inputs.
What input configurations does the ADS1258 support?
The analog input multiplexer supports 16 single-ended inputs or 8 differential inputs. The full-scale input voltage is specified as ±1.06 VREF for VIN equal to ADCINP minus ADCINN.
What data rates are specified for ADS1258 conversion modes?
In fixed-channel mode, the ADS1258 data rate is specified from 1.953 to 125 kSPS. In auto-scan mode, the specified data-rate range is 1.805 to 23.739 kSPS.
What digital interface and GPIO resources are available?
The ADS1258 uses a SPI-compatible serial interface with timing parameters for SCLK, CS, DIN, DOUT, and DRDY. It also provides 8 general-purpose inputs/outputs on GPIO[7:0].
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 13, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.