Specifications
| Type | Description |
|---|---|
| Part Number | CDCE937 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | PW TSSOP-20, 6.50 mm x 6.40 mm nominal package size |
| Component Type | Other |
| Output Clock Count | Up to 7 outputs; generated from a single input frequency |
| PLL Count | 3 PLLs; CDCEx937 device family member |
| Maximum Programmable Output Frequency | 230 MHz; each output programmable in-system |
| External Crystal Frequency Range | 8 MHz to 32 MHz; external crystal input |
| Crystal Input Frequency | 8 MHz min, 27 MHz nom, 32 MHz max; fundamental mode crystal input |
| VCXO Pull Range | ±120 ppm min, ±150 ppm typ; 0 V <= Vctrl <= 1.8 V; depends on crystal and capacitance |
| On-Chip Load Capacitance | 0 pF to 20 pF; at Xin and Xout |
| Device Supply Voltage | 1.7 V min, 1.8 V nom, 1.9 V max; VDD recommended operating condition |
| Output Supply Voltage | 2.3 V to 3.6 V; CDCE937 Vddout recommended operating condition |
| Output Supply Voltage | 1.7 V to 1.9 V; CDCEL937 Vddout recommended operating condition |
| Low-Level Input Voltage | 0.3 x VDD max; LVCMOS input |
| High-Level Input Voltage | 0.7 x VDD min; LVCMOS input |
| Input Voltage Threshold | 0.5 x VDD; LVCMOS input |
| Input Voltage | 0 V to 1.9 V; S0 input |
| Input Voltage | 0 V to 3.6 V; S1, S2, SDA, SCL inputs; VI(thresh)=0.5 VDD |
| CLK Input Voltage | 0 V to 1.9 V; CLK input |
| Output Current | ±12 mA; Vddout = 3.3 V |
| Output Current | ±10 mA; Vddout = 2.5 V |
| Output Current | ±8 mA; Vddout = 1.8 V |
| Output Load | 10 pF; LVCMOS output load |
| Operating Free-Air Temperature | -40°C to 85°C; recommended operating condition |
| Absolute Maximum Supply Voltage | -0.5 V to 2.5 V; VDD over operating free-air temperature range |
| Absolute Maximum Input Voltage | -0.5 V to VDD + 0.5 V; VI; SDA and SCL can go up to 3.6 V per recommended operating conditions |
| Absolute Maximum Output Voltage | -0.5 V to Vddout + 0.5 V; VO |
| Continuous Output Current | 50 mA max; IO absolute maximum rating |
| Junction Temperature | 125°C max; TJ absolute maximum rating |
| Storage Temperature | -65°C to 150°C; Tstg absolute maximum rating |
| HBM ESD Rating | ±2000 V; human-body model per ANSI/ESDA/JEDEC JS-001 |
| CDM ESD Rating | ±1500 V; charged-device model per JEDEC JESD22-C101 |
| VCO Frequency Range | 80 MHz to 230 MHz; PLL VCO |
| LVCMOS Output Frequency | 230 MHz max; Vddout = 3.3 V |
| LVCMOS Output Frequency | 230 MHz max; Vddout = 1.8 V |
| Supply Current | 29 mA; all outputs off, f(VCO)=135 MHz, f(CLK)=27 MHz, all PLLs on |
| Output Supply Current | 3.1 mA; CDCE937, no load, all outputs on, VDDOUT=3.3 V, fOUT=27 MHz |
| Output Supply Current | 1.5 mA; CDCEL937, no load, all outputs on, VDDOUT=1.8 V, fOUT=27 MHz |
| Power-Down Current | 50 µA; every circuit powered down except SDA/SCL, fIN=0 MHz, VDD=1.9 V |
| Power-Up Control Supply Threshold | 0.85 V min, 1.45 V max; VDD threshold for power-up control circuit |
| LVCMOS Input Current | ±5 µA; VI=0 V or VDD, VDD=1.9 V |
| Input Capacitance | 6 pF; Xin/CLK, VI(Clk)=0 V or VDD |
| Input Capacitance | 2 pF; Xout, VI(Xout)=0 V or VDD |
| Input Capacitance | 3 pF; S0/S1/S2, VIS=0 V or VDD |
| Output Duty Cycle | 45% min, 55% max; fVCO=100 MHz, Pdiv=1 |
| Thermal Resistance Junction-to-Ambient | 89.04°C/W; PW TSSOP-20 package |
| Datasheet Status | request_only |
Product Overview
The CDCE937 is a Texas Instruments programmable LVCMOS clock generator for Signal_Chain designs that need multiple clock outputs derived from one input frequency. The device family member includes 3 PLLs and supports up to 7 outputs, with each output programmable in-system up to 230 MHz. The PLL VCO range is specified from 80 MHz to 230 MHz.
Clock input options include an external crystal frequency range of 8 MHz to 32 MHz, with fundamental mode crystal input specified at 8 MHz minimum, 27 MHz nominal, and 32 MHz maximum. VCXO pull range is specified at ±120 ppm minimum and ±150 ppm typical for 0 V <= Vctrl <= 1.8 V, depending on crystal and capacitance. On-chip load capacitance at Xin and Xout is programmable from 0 pF to 20 pF.
The part is supplied in a PW TSSOP-20 package with a 6.50 mm x 6.40 mm nominal package size. Recommended operating conditions include 1.7 V to 1.9 V VDD, 2.3 V to 3.6 V CDCE937 Vddout, and -40°C to 85°C operating free-air temperature.
Key Features
- Up to 7 clock outputs from one input frequency
- Three PLLs in the CDCEx937 device family
- Each output programmable in-system up to 230 MHz
- External crystal input range from 8 MHz to 32 MHz
- PLL VCO frequency range from 80 MHz to 230 MHz
- Programmable 0 pF to 20 pF Xin/Xout load capacitance
- CDCE937 Vddout operating range from 2.3 V to 3.6 V
- LVCMOS output frequency rated to 230 MHz at 1.8 V
- Power-down current specified at 50 µA
- PW TSSOP-20 package thermal resistance of 89.04°C/W
Typical Applications
- Programmable LVCMOS clock generation
- Multi-output clock distribution
- Crystal-referenced timing circuits
- PLL-based frequency synthesis
- VCXO-controlled clock adjustment
- Embedded system clock trees
- Signal-chain timing support
Procurement Notes
When requesting a quote for CDCE937, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
How many outputs does the CDCE937 provide from one input frequency?
The CDCE937 can generate up to 7 outputs from a single input frequency. It is part of the CDCEx937 family and includes 3 PLLs for programmable LVCMOS clock generation.
What output frequency range is specified for the CDCE937?
Each output is programmable in-system up to 230 MHz. The LVCMOS output frequency is also specified at 230 MHz maximum with Vddout at 3.3 V and at 1.8 V.
What supply ranges apply to the CDCE937?
The recommended VDD operating range is 1.7 V minimum, 1.8 V nominal, and 1.9 V maximum. For the CDCE937, Vddout is specified from 2.3 V to 3.6 V.
What crystal input range does the CDCE937 support?
The external crystal input frequency range is 8 MHz to 32 MHz. For fundamental mode crystal input, the extracted specification lists 8 MHz minimum, 27 MHz nominal, and 32 MHz maximum.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 7, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.