Specifications
| Type | Description |
|---|---|
| Part Number | CDCE949 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package Case | PW (TSSOP, 24), 7.8 mm × 6.4 mm |
| Number of PLLs | 4; CDCEx949 family |
| Number of Outputs | 9; CDCEx949 family |
| Output Frequency | up to 230 MHz; each programmable output |
| Input Crystal Frequency | 8 MHz to 32 MHz; external crystal input |
| LVCMOS Input Frequency | up to 160 MHz; single-ended LVCMOS input |
| VCXO Pull Range | ±150 ppm; on-chip VCXO |
| Period Jitter | 60 ps typ; low-noise PLL core |
| Output Supply Voltage | 3.3 V and 2.5 V; CDCE949 |
| Output Supply Voltage | 1.8 V; CDCEL949 |
| Device Core Supply | 1.8 V |
| Operating Temperature | -40°C to 85°C; operating free-air temperature |
| Programmable Control Inputs | 3; S0, S1, S2 user-definable inputs |
| Spread Spectrum Clocking | Center-spread or down-spread; all PLLs support SSC |
| On-Chip Load Capacitance | 0 pF to 20 pF; programmable crystal load capacitance |
| Serial Interface | 2-wire SDA/SCL; device settings programming interface |
| Package | PW (TSSOP, 24); CDCE949 and CDCEL949 |
| Package Size | 7.8 mm × 6.4 mm; nominal length × width including pins |
| VDD Pins | Pins 3, 13; 1.8 V power supply for device |
| VDDOUT Pins | Pins 6, 10, 17; output supply pins |
| Ground Pins | Pins 5, 9, 14, 20 |
| Clock Input Pin | Pin 1; Xin/CLK crystal oscillator input or LVCMOS clock input |
| Crystal Output Pin | Pin 24; Xout crystal oscillator output; leave open or pull up when not used |
| VCXO Control Pin | Pin 4; VCtrl control voltage input; leave open or pull up when not used |
| Output Pins | Y1 pin 21, Y2 pin 19, Y3 pin 18, Y4 pin 7, Y5 pin 8, Y6 pin 16, Y7 pin 15, Y8 pin 11, Y9 pin 12 |
| Absolute Maximum VDD | -0.5 V to 2.5 V |
| Absolute Maximum Input Voltage | -0.5 V to VDD + 0.5 V; SDA and SCL can go up to 3.6 V per recommended conditions |
| Absolute Maximum Output Voltage | -0.5 V to VDDOUT + 0.5 V |
| Absolute Maximum Input Current | 20 mA; VI < 0 or VI > VDD |
| Continuous Output Current | 50 mA; absolute maximum rating |
| Junction Temperature | 125°C max; absolute maximum rating |
| Storage Temperature | -65°C to 150°C; absolute maximum rating |
| ESD HBM | ±2000 V; human-body model, ANSI/ESDA/JEDEC JS-001 |
| ESD CDM | ±1500 V; charged-device model, JEDEC JESD22-C101 |
| Recommended VDD | 1.7 V min, 1.8 V nom, 1.9 V max |
| Recommended VDDOUT | 2.3 V to 3.6 V; CDCE949 output Yx supply voltage |
| Recommended VDDOUT | 1.7 V to 1.9 V; CDCEL949 output Yx supply voltage |
| LVCMOS Low-Level Input Voltage | 0.3 × VDD max; VIL |
| LVCMOS High-Level Input Voltage | 0.7 × VDD min; VIH |
| LVCMOS Input Threshold | 0.5 × VDD; VI(thresh) |
| S0 Input Voltage | 0 V to 1.9 V; VIS input voltage |
| S1/S2/SDA/SCL Input Voltage | 0 V to 3.6 V; VIS input voltage, VIthresh = 0.5 × VDD |
| CLK Input Voltage | 0 V to 1.9 V; VICLK |
| Output Current | ±12 mA; VDDOUT = 3.3 V |
| Output Current | ±10 mA; VDDOUT = 2.5 V |
| Output Current | ±8 mA; VDDOUT = 1.8 V |
| Output Load | 10 pF; LVCMOS output load |
| Crystal Input Frequency | 8 MHz min, 27 MHz nom, 32 MHz max; fundamental mode crystal and VCXO |
| Crystal ESR | 100 Ω max; effective series resistance |
| VCXO Pulling Range | ±120 ppm min, ±150 ppm typ; 0 V ≤ VCtrl ≤ 1.8 V |
| Frequency Control Voltage | 0 V to VDD; VCtrl |
| Pullability Ratio | 220; C0/C1 |
| On-Chip Load Capacitance | 0 pF to 20 pF; at Xin and Xout |
| Thermal Resistance Junction-to-Ambient | 91°C/W; PW TSSOP-24, airflow 0 LFM |
| Thermal Resistance Junction-to-Ambient | 75°C/W; PW TSSOP-24, airflow 150 LFM |
| Thermal Resistance Junction-to-Ambient | 74°C/W; PW TSSOP-24, airflow 200 LFM |
| Thermal Resistance Junction-to-Case Top | 0.5°C/W; PW TSSOP-24 |
| Thermal Resistance Junction-to-Board | 52°C/W; PW TSSOP-24 |
| Supply Current | 38 mA typ; all outputs off, fCLK = 27 MHz, all PLLs on, fVCO = 135 MHz |
| Supply Current Per PLL | 9 mA typ; all outputs off, fCLK = 27 MHz, fVCO = 135 MHz |
| Output Supply Current | 4 mA typ; CDCE949, no load, all outputs on, VDDOUT = 3.3 V, fout = 27 MHz |
| Output Supply Current | 2 mA typ; CDCEL949, no load, all outputs on, VDDOUT = 1.8 V, fout = 27 MHz |
| Power-Down Current | 50 µA max; every circuit powered down except SDA/SCL, fIN = 0 MHz, VDD = 1.9 V |
| Power-Up Control Threshold | 0.85 V min, 1.45 V max; VDD threshold for power-up control circuit |
| PLL VCO Frequency Range | 80 MHz to 230 MHz; fVCO |
| LVCMOS Output Frequency | 230 MHz max; fOUT |
| LVCMOS Input Clamp Voltage | -1.2 V min; VDD = 1.7 V, II = -18 mA |
| LVCMOS Input Current | ±5 µA max; VI = 0 V or VDD, VDD = 1.9 V |
| S0/S1/S2 High-Level Input Current | 5 µA max; VI = VDD, VDD = 1.9 V |
| S0/S1/S2 Low-Level Input Current | -4 µA max; VI = 0 V, VDD = 1.9 V |
| Xin/CLK Input Capacitance | 6 pF typ; VICLK = 0 V or VDD |
| Xout Input Capacitance | 2 pF typ; VI = 0 V or VDD |
| S0/S1/S2 Input Capacitance | 3 pF typ; VIS = 0 V or VDD |
| LVCMOS High-Level Output Voltage | 2.9 V min; CDCE949, VDDOUT = 3 V, IOH = -0.1 mA |
| LVCMOS High-Level Output Voltage | 2.4 V min; CDCE949, VDDOUT = 3 V, IOH = -8 mA |
| LVCMOS High-Level Output Voltage | 2.2 V min; CDCE949, VDDOUT = 3 V, IOH = -12 mA |
| LVCMOS Low-Level Output Voltage | 0.1 V max; CDCE949, VDDOUT = 3 V, IOL = 0.1 mA |
| LVCMOS Low-Level Output Voltage | 0.5 V max; CDCE949, VDDOUT = 3 V, IOL = 8 mA |
| LVCMOS Low-Level Output Voltage | 0.8 V max; CDCE949, VDDOUT = 3 V, IOL = 12 mA |
| Datasheet Status | request_only |
Product Overview
Input options include an external crystal from 8 MHz to 32 MHz or a single-ended LVCMOS input up to 160 MHz. The on-chip VCXO provides ±150 ppm typical pull range, with frequency control through the VCtrl pin from 0 V to VDD. All PLLs support center-spread or down-spread spread-spectrum clocking.
Key Features
- 4 PLLs in the CDCEx949 device family
- 9 programmable LVCMOS outputs available
- Programmable output frequency up to 230 MHz
- External crystal input from 8 MHz to 32 MHz
- Single-ended LVCMOS input supports up to 160 MHz
- On-chip VCXO with ±150 ppm typical pull range
- 60 ps typical period jitter from low-noise PLL core
- 2-wire SDA/SCL interface for device settings
- Center-spread or down-spread SSC on all PLLs
- Programmable crystal load capacitance from 0 pF to 20 pF
Typical Applications
- Programmable LVCMOS clock generation
- PLL frequency synthesis
- Multi-output clock distribution
- VCXO-controlled timing
- Spread-spectrum clocking
- Crystal-based clock generation
- 2-wire programmable timing configuration
Procurement Notes
When requesting a quote for CDCE949, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
How many PLLs and outputs does the CDCE949 provide?
The CDCEx949 family provides 4 PLLs and 9 programmable LVCMOS outputs. Each programmable output supports operation up to 230 MHz, with the PLL VCO frequency range specified from 80 MHz to 230 MHz.
What input clock sources can the CDCE949 use?
The device supports an external crystal input from 8 MHz to 32 MHz. It also accepts a single-ended LVCMOS clock input up to 160 MHz on the Xin/CLK input pin.
What supply voltages apply to CDCE949 outputs?
The device core supply is 1.8 V. For CDCE949, the output supply voltage is specified as 3.3 V and 2.5 V, with recommended VDDOUT operating from 2.3 V to 3.6 V.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 7, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.