Specifications
| Type | Description |
|---|---|
| Part Number | DAC8554 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | TSSOP-16, package designator PW |
| Resolution | 16 bits; condition: Static performance; source page: 2 |
| Relative Accuracy | typ 4 LSB, max 12 LSB; condition: Measured by line passing through codes 485 and 64741; source page: 2 |
| Differential Nonlinearity | typ 0.25 LSB, max 1 LSB; condition: 16-bit monotonic; source page: 2 |
| Zero-Scale Error | typ 2 mV, max 12 mV; condition: Measured by line passing through codes 485 and 64741; source page: 2 |
| Zero-Scale Error Drift | typ 5 uV/°C; condition: VDD=2.7 V to 5.5 V, -40°C to +105°C; source page: 2 |
| Full-Scale Error | typ 0.3% FSR, max 0.5% FSR; condition: AVDD=5 V, VREF=4.99 V and AVDD=2.7 V, VREF=2.69 V; source page: 2 |
| Gain Error | typ 0.05% FSR, max 0.15% FSR; condition: AVDD=5 V, VREF=4.99 V and AVDD=2.7 V, VREF=2.69 V; source page: 2 |
| Gain Temperature Coefficient | typ 1 ppm FSR/°C; condition: VDD=2.7 V to 5.5 V, -40°C to +105°C; source page: 2 |
| Power-Supply Rejection Ratio | typ 0.75 mV/V; condition: RL=2 kOhm, CL=200 pF; source page: 2 |
| Output Voltage Range | 0 V to VREFH; condition: Output characteristics; source page: 2 |
| Output Voltage Settling Time | typ 8 us, max 10 us; condition: To ±0.003% FSR, 0200h to FD00h, RL=2 kOhm, 0 pF < CL < 200 pF; source page: 2 |
| Output Voltage Settling Time | typ 12 us; condition: RL=2 kOhm, CL=500 pF; source page: 2 |
| Slew Rate | typ 1.8 V/us; condition: Output characteristics; source page: 3 |
| Capacitive Load Stability | typ 470 pF; condition: RL=infinity; source page: 3 |
| Capacitive Load Stability | typ 1000 pF; condition: RL=2 kOhm; source page: 3 |
| Code Change Glitch Impulse | typ 0.15 nV-s; condition: 1 LSB change around major carry; source page: 3 |
| Digital Feedthrough | typ 0.15 nV-s; condition: Output characteristics; source page: 3 |
| DC Crosstalk | typ 0.25 LSB; condition: Full-scale swing on adjacent channel, AVDD=5 V, VREF=4.096 V; source page: 3 |
| AC Crosstalk | typ -100 dB; condition: 1 kHz sine wave; source page: 3 |
| DC Output Impedance | typ 1 Ohm; condition: At mid-point input; source page: 3 |
| Short-Circuit Current | typ 50 mA; condition: AVDD=5 V; source page: 3 |
| Short-Circuit Current | typ 20 mA; condition: AVDD=3 V; source page: 3 |
| Power-Up Time | typ 2.5 us; condition: Coming out of power-down mode, AVDD=5 V; source page: 3 |
| Power-Up Time | typ 5 us; condition: Coming out of power-down mode, AVDD=3 V; source page: 3 |
| SNR | typ 95 dB; condition: BW=20 kHz, AVDD=5 V, FOUT=1 kHz, first 19 harmonics removed for SNR calculation; source page: 3 |
| THD | typ -85 dB; condition: BW=20 kHz, AVDD=5 V, FOUT=1 kHz; source page: 3 |
| SFDR | typ 87 dB; condition: BW=20 kHz, AVDD=5 V, FOUT=1 kHz; source page: 3 |
| SINAD | typ 84 dB; condition: BW=20 kHz, AVDD=5 V, FOUT=1 kHz; source page: 3 |
| VREFH Voltage | min 0 V, max AVDD; condition: VREFL < VREFH, AVDD - (VREFH + VREFL)/2 > 1.2 V; source page: 3 |
| VREFL Voltage | min 0 V, max AVDD/2; condition: VREFL < VREFH, AVDD - (VREFH + VREFL)/2 > 1.2 V; source page: 3 |
| Reference Input Current | typ 180 uA, max 250 uA; condition: VREFL=GND, VREFH=AVDD=5 V; source page: 3 |
| Reference Input Current | typ 120 uA, max 200 uA; condition: VREFL=GND, VREFH=AVDD=3 V; source page: 3 |
| Reference Input Impedance | typ 31 kOhm; condition: VREFL < VREFH; source page: 3 |
| Logic Input Low Voltage | max 0.3 × IOVDD; condition: 2.7 V <= IOVDD <= 5.5 V; source page: 3 |
| Logic Input Low Voltage | max 0.1 × IOVDD; condition: 1.8 V <= IOVDD <= 2.7 V; source page: 3 |
| Logic Input High Voltage | min 0.7 × IOVDD; condition: 2.7 V <= IOVDD <= 5.5 V; source page: 3 |
| Logic Input High Voltage | min 0.95 × IOVDD; condition: 1.8 V <= IOVDD < 2.7 V; source page: 3 |
| Pin Capacitance | typ 3 pF; condition: Logic inputs; source page: 3 |
| Analog Supply Voltage | min 2.7 V, max 5.5 V; condition: AVDD power requirement; source page: 3 |
| Digital I/O Supply Voltage | min 1.8 V, max 5.5 V; condition: IOVDD power requirement; source page: 3 |
| Digital I/O Supply Current | typ 10 uA, max 20 uA; condition: Input code=32768, no load, reference current not included; source page: 3 |
| Normal-Mode Supply Current | typ 0.65 mA, max 0.95 mA; condition: AVDD=3.6 V to 5.5 V, VIH=IOVDD and VIL=GND; source page: 3 |
| Normal-Mode Supply Current | typ 0.6 mA, max 0.9 mA; condition: AVDD=2.7 V to 3.6 V; source page: 3 |
| Power-Down Supply Current | typ 0.7 uA, max 2 uA; condition: All power-down modes, AVDD=3.6 V to 5.5 V, VIH=IOVDD and VIL=GND; source page: 3 |
| Power-Down Supply Current | typ 0.4 uA, max 2 uA; condition: All power-down modes, AVDD=2.7 V to 3.6 V; source page: 3 |
| Power Efficiency | typ 89%; condition: IOUT/IDD, IL=2 mA, AVDD=5 V; source page: 3 |
| Specified Temperature Range | min -40°C, max +105°C; condition: Specified performance; source page: 3 |
| Maximum SCLK Frequency | 50 MHz; condition: IOVDD=AVDD=3.6 V to 5.5 V; source page: 5 |
| Maximum SCLK Frequency | 25 MHz; condition: IOVDD=AVDD=2.7 V to 3.6 V; source page: 5 |
| SCLK Cycle Time | min 40 ns; condition: IOVDD=AVDD=2.7 V to 3.6 V; source page: 5 |
| SCLK Cycle Time | min 20 ns; condition: IOVDD=AVDD=3.6 V to 5.5 V; source page: 5 |
| SCLK High Time | min 20 ns; condition: IOVDD=AVDD=2.7 V to 3.6 V; source page: 5 |
| SCLK High Time | min 10 ns; condition: IOVDD=AVDD=3.6 V to 5.5 V; source page: 5 |
| SCLK Low Time | min 20 ns; condition: IOVDD=AVDD=2.7 V to 3.6 V; source page: 5 |
| SCLK Low Time | min 10 ns; condition: IOVDD=AVDD=3.6 V to 5.5 V; source page: 5 |
| Data Setup Time | min 5 ns; condition: IOVDD=AVDD=2.7 V to 5.5 V; source page: 5 |
| Data Hold Time | min 4.5 ns; condition: IOVDD=AVDD=2.7 V to 5.5 V; source page: 5 |
| Minimum SYNC High Time | min 40 ns; condition: IOVDD=AVDD=2.7 V to 3.6 V; source page: 5 |
| Minimum SYNC High Time | min 20 ns; condition: IOVDD=AVDD=3.6 V to 5.5 V; source page: 5 |
| 24th SCLK Falling Edge to SYNC Falling Edge | min 130 ns; condition: IOVDD=AVDD=2.7 V to 5.5 V; source page: 5 |
| Operating Temperature Range | -40°C to +105°C; condition: Absolute maximum ratings; source page: 2 |
| Storage Temperature Range | -65°C to +150°C; condition: Absolute maximum ratings; source page: 2 |
| Junction Temperature Range | max 150°C; condition: TJ max; source page: 2 |
| Thermal Impedance Junction-to-Ambient | 118°C/W; condition: TSSOP-16 package; source page: 2 |
| Thermal Impedance Junction-to-Case | 29°C/W; condition: TSSOP-16 package; source page: 2 |
| ESD Rating HBM | 1500 V; condition: Human body model; source page: 2 |
| ESD Rating CDM | 1000 V; condition: Charged device model; source page: 2 |
| Datasheet Status | request_only |
Product Overview
The DAC8554 is a Texas Instruments 16-bit quad voltage-output DAC for Signal_Chain applications. It is supplied in a TSSOP-16 package, package designator PW, and provides four voltage-output DAC channels with an output range from 0 V to VREFH. Static performance includes 16-bit resolution, typical 4 LSB relative accuracy, 16-bit monotonic differential nonlinearity with 0.25 LSB typical and 1 LSB maximum DNL, and typical 0.05% FSR gain error under the stated reference and supply conditions.
Output behavior is defined by typical 8 us settling time, with a 10 us maximum, to ±0.003% FSR for a 0200h to FD00h transition with RL = 2 kOhm and 0 pF < CL < 200 pF. Additional output parameters include 1.8 V/us typical slew rate, 1 Ohm typical dc output impedance, 0.15 nV-s typical code-change glitch impulse, and -100 dB typical ac crosstalk at a 1 kHz sine wave.
The device operates with AVDD from 2.7 V to 5.5 V and IOVDD from 1.8 V to 5.5 V. Timing limits include maximum SCLK frequency of 50 MHz at 3.6 V to 5.5 V supplies and 25 MHz at 2.7 V to 3.6 V supplies. Specified performance covers -40°C to +105°C, with storage rating from -65°C to +150°C.
Key Features
- 16-bit quad voltage-output DAC architecture
- TSSOP-16 package with PW package designator
- 0 V to VREFH output voltage range
- 16-bit monotonic DNL, 0.25 LSB typical
- 8 us typical settling to ±0.003% FSR
- 1.8 V/us typical output slew rate
- 2.7 V to 5.5 V analog supply range
- 1.8 V to 5.5 V digital I/O supply range
- 50 MHz maximum SCLK at 3.6 V to 5.5 V
- -40°C to +105°C specified performance range
Typical Applications
- Precision multi-channel voltage outputs
- Signal-chain output adjustment
- Reference-based voltage generation
- Low-power analog output stages
- Digitally timed DAC updates
- Temperature-rated industrial signal paths
Procurement Notes
When requesting a quote for DAC8554, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What is the DAC8554 resolution and channel type?
The DAC8554 is specified as a 16-bit quad voltage-output DAC. Its static performance includes 16-bit resolution, and the output voltage range is defined from 0 V to VREFH.
What supply ranges does the DAC8554 support?
The analog supply voltage range is 2.7 V to 5.5 V. The digital I/O supply voltage range is 1.8 V to 5.5 V, with separate logic input thresholds specified for lower and higher IOVDD ranges.
What settling time is specified for the DAC8554 output?
The output voltage settling time is typically 8 us and 10 us maximum to ±0.003% FSR for a 0200h to FD00h transition with RL = 2 kOhm and 0 pF < CL < 200 pF.
What package is used for the DAC8554?
The provided package information identifies the DAC8554 as using a TSSOP-16 package with package designator PW. Thermal impedance values are specified for this TSSOP-16 package.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 13, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.