Specifications
| Type | Description |
|---|---|
| Part Number | DRV8802 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Component Type | Power_IC |
| Package / Case | 28-pin HTSSOP (PWP) with PowerPAD, 9.70 mm x 4.40 mm body |
| Operating supply voltage range | 8.2 to 45 V; motor supply VM, recommended operating condition |
| Maximum drive current | 1.6 A peak or 1.1 A RMS per H-bridge; with proper heatsinking at 24 V and 25°C |
| Continuous motor drive output current | 0 to 1.6 A; absolute maximum rating, power dissipation and thermal limits must be observed |
| Power supply voltage absolute maximum | -0.3 to 47 V; VMx over operating free-air temperature range |
| Power supply ramp rate | 0 to 1 V/us; VMx absolute maximum rating |
| Digital pin voltage absolute maximum | -0.5 to 7 V; over operating free-air temperature range |
| VREF input voltage absolute maximum | -0.3 to 4 V; over operating free-air temperature range |
| ISENSE pin voltage absolute maximum | -0.8 to 0.8 V; transients of +/-1 V for less than 25 ns acceptable |
| Operating virtual junction temperature | -40 to 150°C; absolute maximum rating |
| Operating ambient temperature | -40 to 85°C; absolute maximum rating |
| Storage temperature | -60 to 150°C; absolute maximum rating |
| HBM ESD rating | +/-2000 V; ANSI/ESDA/JEDEC JS-001, all pins |
| CDM ESD rating | +/-500 V; JEDEC JESD22-C101, all pins |
| VREF recommended input voltage | 1 to 3.5 V; operational between 0 V and 1 V but accuracy degraded |
| V3P3OUT load current | 1 mA max; recommended operating condition |
| Junction-to-ambient thermal resistance | 38.9°C/W; PWP HTSSOP, 28 pins |
| Junction-to-case top thermal resistance | 23.3°C/W; PWP HTSSOP, 28 pins |
| Junction-to-board thermal resistance | 21.2°C/W; PWP HTSSOP, 28 pins |
| Junction-to-top characterization parameter | 0.8°C/W; PWP HTSSOP, 28 pins |
| Junction-to-board characterization parameter | 20.9°C/W; PWP HTSSOP, 28 pins |
| Junction-to-case bottom thermal resistance | 2.6°C/W; PWP HTSSOP, 28 pins |
| VM operating supply current | 5 mA typ, 8 mA max; VM=24 V, fPWM < 50 kHz |
| VM sleep mode supply current | 10 uA typ, 20 uA max; VM=24 V |
| VM undervoltage lockout voltage | 7.8 V typ, 8.2 V max; VM rising |
| V3P3OUT voltage | 3.18 V min, 3.3 V typ, 3.42 V max; IOUT=0 to 1 mA, VM=24 V, TJ=25°C |
| V3P3OUT voltage | 3.1 V min, 3.3 V typ, 3.5 V max; IOUT=0 to 1 mA |
| Logic input low voltage | 0.6 V min, 0.7 V max; logic-level inputs |
| Logic input high voltage | 2 V min, 5.25 V max; logic-level inputs |
| Logic input hysteresis | 0.45 V typ; logic-level inputs |
| Logic input low current | -20 to 20 uA; VIN=0 V |
| Logic input high current | 100 uA max; VIN=3.3 V |
| nFAULT output low voltage | 0.5 V max; IO=5 mA, open-drain output |
| nFAULT output high leakage current | 1 uA max; VO=3.3 V, open-drain output |
| DECAY input low threshold voltage | 0 to 0.8 V; for slow decay mode |
| DECAY input high threshold voltage | 2 V min; for fast decay mode |
| DECAY input current | +/-40 uA; DECAY input |
| High-side FET on resistance | 0.63 ohm typ; VM=24 V, IO=1 A, TJ=25°C |
| High-side FET on resistance | 0.76 ohm typ, 0.9 ohm max; VM=24 V, IO=1 A, TJ=85°C |
| Low-side FET on resistance | 0.65 ohm typ; VM=24 V, IO=1 A, TJ=25°C |
| Low-side FET on resistance | 0.78 ohm typ, 0.9 ohm max; VM=24 V, IO=1 A, TJ=85°C |
| Off-state leakage current | -20 to 20 uA; H-bridge FETs |
| Internal PWM frequency | 50 kHz typ; motor driver |
| Current sense blanking time | 3.75 us typ; motor driver |
| Rise time | 100 ns typ, 360 ns max; VM=24 V |
| Fall time | 80 ns typ, 250 ns max; VM=24 V |
| Dead time | 400 ns typ; motor driver |
| Input deglitch time | 1.3 us min, 2.9 us max; motor driver |
| Overcurrent protection trip level | 1.8 to 5 A; protection circuits |
| Thermal shutdown temperature | 150°C min, 160°C typ, 180°C max; die temperature |
| xVREF input current | -3 to 3 uA; xVREF=3.3 V |
| xISENSE trip voltage at 100% current | 635 mV min, 660 mV typ, 685 mV max; xVREF=3.3 V, 100% current setting |
| xISENSE trip voltage at 71% current | 445 mV min, 469 mV typ, 492 mV max; xVREF=3.3 V, 71% current setting |
| xISENSE trip voltage at 38% current | 225 mV min, 251 mV typ, 276 mV max; xVREF=3.3 V, 38% current setting |
| Current sense amplifier gain | 5 V/V; reference only |
| Current control levels | 00=100%, 01=71%, 10=38%, 11=0; AI0/AI1 and BI0/BI1 bridge current setting inputs |
| Decay mode control | Low=brake/slow decay, high=coast/fast decay; DECAY pin logic state |
| Sleep mode control | Logic high enables device, logic low enters low-power sleep mode; nSLEEP input |
| Fault indication | Logic low during fault condition; nFAULT for overtemperature or overcurrent fault |
| 3.3 V regulator bypass capacitor | 0.47 uF, 6.3 V ceramic capacitor; V3P3OUT bypass to GND |
| Charge pump flying capacitor | 0.01 uF, 50 V capacitor; between CP1 and CP2 |
| VCP external components | 0.1 uF, 16 V ceramic capacitor and 1 Mohm resistor to VM; high-side gate drive voltage pin |
| Datasheet Status | request_only |
Product Overview
The DRV8802 is a Texas Instruments dual H-bridge DC motor driver in the Power_Management category. It is specified for an 8.2 to 45 V recommended motor supply range and can drive up to 1.6 A peak or 1.1 A RMS per H-bridge when thermal design and heatsinking are appropriate at 24 V and 25°C.
Control functions include bridge current settings of 100%, 71%, 38%, or 0 through the AI0/AI1 and BI0/BI1 inputs. The DECAY input selects slow decay with a low logic level or fast decay with a high logic level, while nSLEEP enables the device with a logic high and places it in low-power sleep with a logic low.
The package is a 28-pin HTSSOP (PWP) with PowerPAD and a 9.70 mm x 4.40 mm body. Thermal data includes 38.9°C/W junction-to-ambient resistance and 2.6°C/W junction-to-case bottom resistance. External support components include a 0.47 uF V3P3OUT bypass capacitor, a 0.01 uF charge-pump flying capacitor, and VCP components of 0.1 uF plus 1 Mohm to VM.
Key Features
- Dual H-bridge DC motor driver topology
- 8.2 to 45 V recommended VM operating range
- 1.6 A peak per H-bridge with proper heatsinking
- 50 kHz typical internal PWM motor-driver frequency
- Selectable 100%, 71%, 38%, and 0 current levels
- DECAY pin selects slow or fast decay operation
- nSLEEP input supports low-power sleep mode
- nFAULT output reports overtemperature or overcurrent faults
- Integrated 3.3 V V3P3OUT regulator output
- 28-pin HTSSOP PowerPAD package for thermal dissipation
Typical Applications
- Dual DC motor drive stages
- Brushed DC motor control
- 24 V motor supply systems
- Current-regulated motor outputs
- Sleep-controlled motor electronics
- Fault-monitored motor drive boards
- Fast or slow decay drive designs
Procurement Notes
When requesting a quote for DRV8802, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What supply voltage range does DRV8802 support?
DRV8802 is specified for an 8.2 to 45 V recommended motor supply range on VM. The absolute maximum VMx supply rating is -0.3 to 47 V, with a VMx ramp-rate limit of 0 to 1 V/us.
How much output current can each H-bridge drive?
With proper heatsinking at 24 V and 25°C, each H-bridge is rated for 1.6 A peak or 1.1 A RMS. The continuous motor drive output current absolute maximum is listed as 0 to 1.6 A, subject to power dissipation and thermal limits.
What package is used for the DRV8802?
DRV8802 is supplied in a 28-pin HTSSOP PWP package with PowerPAD. The package body measures 9.70 mm x 4.40 mm and has thermal metrics including 38.9°C/W junction-to-ambient resistance.
What current regulation settings are available?
The bridge current setting inputs AI0/AI1 and BI0/BI1 select four current levels: 00 for 100%, 01 for 71%, 10 for 38%, and 11 for 0. The current sense amplifier gain is listed as 5 V/V.
How does DRV8802 indicate fault conditions?
The nFAULT pin is an open-drain output that goes logic low during overtemperature or overcurrent fault conditions. Its output low voltage is specified as 0.5 V maximum at 5 mA, with 1 uA maximum high leakage at 3.3 V.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.