Specifications
| Type | Description |
|---|---|
| Part Number | DRV8881 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Operating supply voltage range | 6.5 to 45 V; recommended operating conditions, VM |
| Absolute maximum supply voltage | -0.3 to 50 V; VM referenced to GND |
| Power supply voltage ramp rate | 0 to 2 V/us; VM ramp rate, absolute maximum ratings |
| Peak drive current | 2.5 A peak per H-bridge; with proper PCB ground plane for thermal dissipation, VM=24 V, TA=25°C |
| Motor RMS current per H-bridge | 0 to 1.4 A; recommended operating conditions |
| Output stage | Two N-channel power MOSFET H-bridge drivers; device description |
| Supported motor types | Bipolar stepper motor; single or dual brushed-DC motor |
| Control interface options | PHASE/ENABLE (DRV8881E); PWM (DRV8881P) |
| Decay modes | Smart tune, mixed decay, slow decay, fast decay; smart tune available on DRV8881E only |
| Configurable PWM chopping off-time | 10, 20, or 30 us; TOFF tri-level pin setting |
| Internal regulator voltage | 2.9 V min, 3.3 V typ, 3.6 V max; V3P3 external load 0 to 10 mA |
| Internal regulator external load current | 0 to 10 mA; power dissipation and thermal limits must be observed |
| Sleep-mode supply current at 25°C | 28 uA typ; nSLEEP low, VM=24 V, TA=25°C |
| Sleep-mode supply current at 125°C | 77 uA typ; nSLEEP low, VM=24 V, TA=125°C |
| Operating supply current | 8 mA typ, 18 mA max; nSLEEP high, ENABLE high, no motor load, VM=24 V |
| Sleep time | 100 us typ; nSLEEP low to sleep mode |
| Wake-up time | 1.5 ms typ; nSLEEP high to output transition |
| Turn-on time | 1.5 ms typ; VM > VUVLO to output transition |
| Digital pin voltage range | 0 to 5.3 V; recommended operating conditions, VIN |
| Reference RMS voltage range | 0.3 V to V3P3; AVREF, BVREF; operational near 0 to 0.3 V with degraded accuracy |
| Applied PWM signal frequency | 0 to 100 kHz; APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2 |
| Input logic low voltage | 0 to 0.6 V; logic-level inputs |
| Input logic high voltage | 1.6 to 5.3 V; logic-level inputs |
| Input logic hysteresis | 100 mV typ; logic-level inputs |
| Input logic low current | -1 to 1 uA; VIN=0 V |
| Input logic high current | 50 uA typ, 100 uA max; VIN=5.0 V |
| Pulldown resistance | 100 kOhm typ; measured between pin and GND |
| Propagation delay | 450 ns typ; xPH, xEN, xINx input to current change |
| Charge pump voltage above 12 V | VM + 11.5 V typ; VM > 12 V |
| Charge pump voltage below 12 V | 2 x VM - 1.5 V typ; VUVLO < VM < 12 V |
| Charge pump switching frequency | 175 to 715 kHz; VM > VUVLO |
| Charge pump voltage absolute maximum | -0.3 V to VM + 12 V; VCP, CPH referenced to GND |
| Charge pump negative switching pin absolute maximum | -0.3 V to VM; CPL referenced to GND |
| Internal regulator voltage absolute maximum | -0.3 to 3.8 V; V3P3 referenced to GND |
| Control pin voltage absolute maximum | -0.3 to 7.0 V; control pins referenced to GND |
| Reference input pin voltage absolute maximum | -0.3 V to V3P3 + 0.5 V; AVREF, BVREF referenced to GND |
| Continuous phase node pin voltage | -0.7 V to VM + 0.7 V; AOUT1, AOUT2, BOUT1, BOUT2 |
| Continuous shunt amplifier input pin voltage | -0.55 to 0.55 V; AISEN, BISEN; +/-1 V transients for less than 25 ns acceptable |
| Open-drain output current | 0 to 10 mA; nFAULT absolute maximum rating |
| Operating junction temperature | -40 to 150°C; TJ absolute maximum rating |
| Storage temperature | -65 to 150°C; Tstg absolute maximum rating |
| Operating ambient temperature | -40 to 125°C; recommended operating conditions, TA |
| ESD rating, HBM | +/-4000 V; per ANSI/ESDA/JEDEC JS-001 |
| ESD rating, CDM | +/-1000 V; per JEDEC JESD22-C101 |
| Junction-to-ambient thermal resistance | 33.1°C/W HTSSOP; 37.5°C/W WQFN |
| Junction-to-case top thermal resistance | 16.6°C/W HTSSOP; 23.0°C/W WQFN |
| Junction-to-board thermal resistance | 14.4°C/W HTSSOP; 8.0°C/W WQFN |
| Junction-to-case bottom thermal resistance | 1.3°C/W HTSSOP; 1.7°C/W WQFN |
| External VM bypass capacitor | 0.1 uF ceramic per VM pin plus bulk capacitor; capacitor rated for VM |
| Recommended bulk capacitor | 100 uF; bulk electrolytic capacitor from VM to GND, rated for VM |
| VCP capacitor | 0.47 uF ceramic, 16 V; CVCP from VCP to VM |
| Charge pump flying capacitor | 0.1 uF X7R capacitor rated for VM; CSW from CPH to CPL |
| V3P3 bypass capacitor | 0.47 uF ceramic, 6.3 V; CV3P3 from V3P3 to GND |
| nFAULT pullup resistor | >5 kOhm; open-drain nFAULT output pulled up to MCU supply or V3P3 |
| Protection features | VM UVLO, charge pump UVLO, overcurrent protection, automatic OCP retry, thermal shutdown, nFAULT indication |
| Datasheet Status | request_only |
Product Overview
The DRV8881 is a Texas Instruments dual H-bridge motor driver in the Power_Management category. Its output stage uses two N-channel power MOSFET H-bridge drivers and supports bipolar stepper motors as well as single or dual brushed-DC motors. Device variants provide PHASE/ENABLE control on DRV8881E and PWM control on DRV8881P.
The recommended VM operating range is 6.5 to 45 V, with 0 to 1.4 A RMS motor current per H-bridge. Peak current is specified as 2.5 A per H-bridge with proper PCB ground-plane thermal dissipation at VM = 24 V and TA = 25°C. Supported decay modes include smart tune, mixed decay, slow decay, and fast decay, with smart tune available on DRV8881E only.
Package options are 28-pin HTSSOP PowerPAD (PWP) at 9.70 mm x 6.40 mm and 28-pin WQFN PowerPAD (RHR) at 5.50 mm x 3.50 mm. External components include VM bypass and bulk capacitors, VCP and V3P3 capacitors, a charge-pump flying capacitor, and an nFAULT pullup resistor. Protection functions include VM UVLO, charge-pump UVLO, overcurrent protection with automatic retry, thermal shutdown, and nFAULT indication.
Key Features
- 6.5 to 45 V recommended VM operating range
- 2.5 A peak drive current per H-bridge
- 0 to 1.4 A RMS motor current per H-bridge
- Two N-channel power MOSFET H-bridge output stages
- Supports bipolar stepper and brushed-DC motor loads
- PHASE/ENABLE and PWM interface variants available
- Smart tune, mixed, slow, and fast decay modes
- 10, 20, or 30 us PWM chopping off-time
- 3.3 V typical internal regulator output
- 28 uA typical sleep current at 25°C
- 450 ns typical input-to-current propagation delay
- UVLO, OCP retry, thermal shutdown, nFAULT indication
Typical Applications
- Bipolar stepper motor control
- Single brushed-DC motor drives
- Dual brushed-DC motor drives
- PWM-controlled motor stages
- PHASE/ENABLE motor control designs
- PowerPAD motor driver assemblies
Procurement Notes
When requesting a quote for DRV8881, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What supply range does the DRV8881 support?
The DRV8881 recommended VM operating supply range is 6.5 to 45 V. The absolute maximum VM rating is -0.3 to 50 V referenced to GND, with a VM ramp-rate absolute maximum of 0 to 2 V/us.
What motor types can the DRV8881 drive?
The DRV8881 supports bipolar stepper motors and single or dual brushed-DC motors. Its output stage is built from two N-channel power MOSFET H-bridge drivers.
Which control interfaces are available for DRV8881 variants?
The DRV8881E variant uses a PHASE/ENABLE interface, while the DRV8881P variant uses a PWM interface. Applied PWM signal frequency is specified from 0 to 100 kHz on the listed control inputs.
What external capacitors are specified for the DRV8881?
The extracted datasheet facts specify 0.1 uF ceramic bypassing per VM pin plus a 100 uF VM bulk capacitor, a 0.47 uF VCP capacitor, a 0.1 uF X7R charge-pump flying capacitor, and a 0.47 uF V3P3 bypass capacitor.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 22, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.