Specifications
| Type | Description |
|---|---|
| Part Number | DS90C185 |
| Manufacturer | Texas Instruments |
| Product Type | LVDS Serializer |
| Category | Signal Chain |
| Package Case | 48-pin WQFN, 6 mm x 6 mm x 0.8 mm |
| Serializer Function | 24-bit RGB plus 3 video control signals serialized to LVDS-compatible interface; condition: 4 data + clock reduced-width LVDS interface |
| Operating Modes | 24-bit RGB and 18-bit RGB; condition: 18B_MODE pin selects 3D+C or 4D+C mode |
| Maximum Display Resolution | 1400 x 1050 at 60 Hz; condition: SXGA+ display support |
| Throughput | 2.94 Gbps; condition: Serializer throughput |
| Typical Power Dissipation | 50 mW; condition: 75 MHz pixel clock |
| Supply Voltage | 1.71 V min, 1.8 V nom, 1.89 V max; condition: Recommended operating condition, VDD |
| Operating Free-Air Temperature | -10 °C min, +22 °C nom, +70 °C max; condition: Recommended operating condition, TA |
| Supply Noise Voltage | <90 mVPP; condition: Recommended operating condition, VDD noise |
| Differential Load Impedance | 80 Ω min, 100 Ω nom, 120 Ω max; condition: Recommended operating condition |
| Input Clock Frequency | 25 MHz min, 105 MHz max; condition: Recommended operating condition |
| Absolute Maximum Supply Voltage | -0.3 V to +2.5 V; condition: VDD absolute maximum rating |
| Absolute Maximum LVCMOS Input Voltage | -0.5 V to VDD + 0.3 V; condition: Absolute maximum rating |
| Absolute Maximum LVDS Driver Output Voltage | -0.3 V to VDD + 0.3 V; condition: Absolute maximum rating |
| LVDS Output Short Circuit Duration | Continuous; condition: Absolute maximum rating |
| Junction Temperature | +150 °C; condition: Absolute maximum rating |
| Storage Temperature | -65 °C to +150 °C; condition: Absolute maximum rating |
| Lead Temperature | +260 °C; condition: Soldering, 4 seconds |
| Package Thermal Resistance | 26.6 °C/W; condition: θJA package derating above +22 °C |
| ESD Rating HBM | >4 kV; condition: Human Body Model |
| ESD Rating CDM | >1.25 kV; condition: Charged Device Model |
| ESD Rating MM | >250 V; condition: Machine Model |
| High-Level Input Voltage | 0.65 x VDD min; condition: LVCMOS DC specification, VIH |
| Low-Level Input Voltage | 0.35 x VDD max; condition: LVCMOS DC specification, VIL |
| Input Current | -10 µA min, ±1 µA typ, +10 µA max; condition: VIN = 0 V or VIN = VDD, VDD = 1.71 V to 1.89 V |
| Differential Output Voltage | 160 mV min, 300 mV typ, 450 mV max; condition: RL = 100 Ω, VOD_SEL = H |
| Differential Output Voltage Peak-to-Peak | 320 mV min, 600 mV typ, 900 mV max; condition: RL = 100 Ω, VOD_SEL = H |
| Reduced Differential Output Voltage | 115 mV min, 180 mV typ, 300 mV max; condition: RL = 100 Ω, VOD_SEL = L |
| Reduced Differential Output Voltage Peak-to-Peak | 230 mV min, 360 mV typ, 600 mV max; condition: RL = 100 Ω, VOD_SEL = L |
| Change in Differential Output Voltage | 50 mV max; condition: Between complementary output states, RL = 100 Ω |
| Offset Voltage | 0.8 V min, 0.9 V typ, 1.0 V max; condition: LVDS DC specification, VOS |
| Change in Offset Voltage | 50 mV max; condition: Between complementary output states |
| Output Short Circuit Current | -45 mA min, -35 mA typ, -25 mA max; condition: VOS = 0 V, ROUT = 100 Ω |
| Output LVDS Driver Power-Down Current | ±1 mA typ, ±10 mA max; condition: PDB = 0 V |
| Serializer Supply Current Worst Case | 60 mA min, 85 mA max; condition: Checkerboard pattern, f = 105 MHz, RL = 100 Ω, 18B_MODE = L, VOD_SEL = H, VDD = 1.89 V |
| Serializer Supply Current | 31 mA typ; condition: 16 grayscale pattern, RL = 100 Ω, f = 75 MHz, 18B_MODE = L, VOD_SEL = L, VDD = 1.8 V |
| Serializer Supply Current | 41 mA typ; condition: 16 grayscale pattern, RL = 100 Ω, f = 75 MHz, 18B_MODE = L, VOD_SEL = H, VDD = 1.8 V |
| Serializer Supply Current | 28 mA typ; condition: 16 grayscale pattern, RL = 100 Ω, f = 75 MHz, 18B_MODE = H, VOD_SEL = L, VDD = 1.8 V |
| Serializer Supply Current | 36 mA typ; condition: 16 grayscale pattern, RL = 100 Ω, f = 75 MHz, 18B_MODE = H, VOD_SEL = H, VDD = 1.8 V |
| Serializer Supply Current | 33 mA typ; condition: PRBS-7 pattern, RL = 100 Ω, f = 75 MHz, 18B_MODE = L, VOD_SEL = L, VDD = 1.8 V |
| Serializer Supply Current | 45 mA typ; condition: PRBS-7 pattern, RL = 100 Ω, f = 75 MHz, 18B_MODE = L, VOD_SEL = H, VDD = 1.8 V |
| Serializer Supply Current | 29 mA typ; condition: PRBS-7 pattern, RL = 100 Ω, f = 75 MHz, 18B_MODE = H, VOD_SEL = L, VDD = 1.8 V |
| Serializer Supply Current | 38 mA typ; condition: PRBS-7 pattern, RL = 100 Ω, f = 75 MHz, 18B_MODE = H, VOD_SEL = H, VDD = 1.8 V |
| Serializer Power-Down Current | 18 µA typ, 200 µA max; condition: IDDZ |
| TxCLKIN Transition Time | 1.0 ns min, 6.0 ns max; condition: Recommended transmitter input characteristic, TCIT |
| TxCLKIN Period | 9.52 ns min, 40 ns max; condition: Recommended transmitter input characteristic, TCIP |
| TxCLKIN High Time | 0.35T min, 0.5T typ, 0.65T max; condition: Recommended transmitter input characteristic, TCIH |
| TxCLKIN Low Time | 0.35T min, 0.5T typ, 0.65T max; condition: Recommended transmitter input characteristic, TCIL |
| LVDS Low-to-High Transition Time | 0.18 ns typ, 0.5 ns max; condition: Transmitter switching characteristic, guaranteed by characterization |
| LVDS High-to-Low Transition Time | 0.18 ns typ, 0.5 ns max; condition: Transmitter switching characteristic, guaranteed by characterization |
| Transmitter Output Pulse Position Bit 0 | 1 UI; condition: f = 105 MHz |
| Transmitter Output Pulse Position Bit 1 | 2 UI; condition: f = 105 MHz |
| Transmitter Output Pulse Position Bit 2 | 3 UI; condition: f = 105 MHz |
| Transmitter Output Pulse Position Bit 3 | 4 UI; condition: f = 105 MHz |
| Transmitter Output Pulse Position Bit 4 | 5 UI; condition: f = 105 MHz |
| Transmitter Output Pulse Position Bit 5 | 6 UI; condition: f = 105 MHz |
| Transmitter Output Pulse Position Bit 6 | 7 UI; condition: f = 105 MHz |
| Variation in Transmitter Pulse Position | ±0.06 UI; condition: Bit 6 to Bit 0 |
| Required TxIN Setup to TxCLKIN | 0 ns min; condition: TSTC |
| Required TxIN Hold to TxCLKIN | 2.5 ns min; condition: THTC |
| Cycle-to-Cycle Jitter | 0.028 UI typ, 0.035 UI max; condition: f = 105 MHz, guaranteed by characterization |
| Serializer Propagation Delay | 2 x TCIP + 10.54 ns typ, 2 x TCIP + 13.96 ns max; condition: f = 105 MHz |
| TxOUT Channel-to-Channel Skew | 110 ps max; condition: TCCS |
| Transmitter PLL Set Time | 1 ms max; condition: TPLLS |
| Transmitter Power-Down Delay | 100 ns max; condition: TPPD, guaranteed by design |
| LVDS Output Configuration | 4D+C in 24-bit mode; 3D+C in 18-bit mode; condition: 18B_MODE = L for 24-bit RGB, 18B_MODE = H for 18-bit RGB |
| 18-bit Mode TxOUT3 State | TRI-STATE; condition: 18B_MODE = H; TxOUT3 output disabled to save power |
| Clock Input Pin | CLK; condition: 1.8 V LVCMOS input with pulldown |
| R_FB Control Function | 1 = rising-edge clock, 0 = falling-edge clock default; condition: LVCMOS programmable strobe select with pulldown |
| 18B_MODE Control Function | 1 = 3D+C 18-bit RGB mode, 0 = 4D+C 24-bit RGB mode default; condition: Mode configuration input with pulldown |
| VOD_SEL Control Function | 0 = reduced VOD lower power, 1 = normal VOD default; condition: VOD select input with pulldown |
| PDB Control Function | 1 = active, 0 = sleep state default; condition: Power Down Bar input with pulldown |
| Datasheet Status | request_only |
Product Overview
Mode selection is controlled by the 18B_MODE pin: logic low selects 4D+C 24-bit RGB mode, while logic high selects 3D+C 18-bit RGB mode. In 18-bit mode, TxOUT3 is placed in TRI-STATE to reduce power. The R_FB input selects rising-edge or falling-edge clocking, VOD_SEL selects normal or reduced LVDS output swing, and PDB controls active versus sleep state operation.
Key Features
- Serializes 24-bit RGB plus three video controls
- Selectable 24-bit RGB and 18-bit RGB modes
- Supports SXGA+ 1400 x 1050 at 60 Hz
- Provides 2.94 Gbps serializer throughput
- Operates from 1.71 V to 1.89 V VDD
- Accepts 25 MHz to 105 MHz input clock
- Selectable normal or reduced LVDS output voltage
- 18-bit mode disables TxOUT3 in TRI-STATE
- PLL set time specified at 1 ms maximum
- 48-pin WQFN 6 mm x 6 mm package
Typical Applications
- SXGA+ display interfaces
- RGB video serialization
- FPD-Link LVDS transmit paths
- Reduced-width LVDS display links
- 24-bit RGB panel connections
- 18-bit RGB panel connections
Procurement Notes
When requesting a quote for DS90C185, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What interface does the DS90C185 serialize?
The DS90C185 serializes 24-bit RGB plus three video control signals to an LVDS-compatible interface using a reduced-width four data plus clock configuration.
Which RGB modes are supported by DS90C185?
The device supports 24-bit RGB and 18-bit RGB operation. The 18B_MODE pin selects the configuration, with 4D+C used for 24-bit RGB and 3D+C used for 18-bit RGB.
What supply voltage range is recommended?
The recommended VDD operating range is 1.71 V minimum, 1.8 V nominal, and 1.89 V maximum, with recommended VDD supply noise below 90 mVPP.
What package is used for this serializer?
The DS90C185 is specified in a 48-pin WQFN package with 6 mm x 6 mm body dimensions and 0.8 mm package height.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 27, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.