Specifications
| Type | Description |
|---|---|
| Part Number | FDC1004 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Component Type | Sensor |
| Package / Case | WSON (DSC, 10) 3 mm x 3 mm; VSSOP (DGS, 10) 3 mm x 4.9 mm |
| Number of channels | 4; capacitive sensing inputs CIN1-CIN4 |
| Input conversion range | +/-15 pF; capacitive input full-scale range per channel |
| Measurement resolution | 0.5 fF; feature summary |
| Effective resolution | 16 bit; sample rate = 100 S/s; no external capacitance connected |
| Output noise | 33.2 aF/sqrt(Hz); sample rate = 100 S/s; no external capacitance connected |
| Maximum input offset capacitance | 100 pF; per channel, CINn; series resistance at CINn = 0 ohm |
| Absolute error after offset calibration | +/-6 fF; VDD = 3.3 V, TA = 25 degC unless otherwise noted |
| Offset deviation over temperature | 46 fF; -40 degC < T < 125 degC |
| Gain error | 0.2 %; VDD = 3.3 V, TA = 25 degC unless otherwise noted |
| Gain drift vs temperature | -37.5 ppm/degC; -40 degC < T < 125 degC |
| DC power supply rejection | 13.6 fF/V; 3 V < VDD < 3.6 V, single-ended mode, channel vs GND |
| CAPDAC full-scale range | 96.9 pF; CAPDAC |
| CAPDAC offset drift vs temperature | 30 fF; -40 degC < T < 125 degC |
| Excitation frequency | 25 kHz; capacitive excitation |
| AC voltage across capacitance | 2.4 Vpp; capacitive excitation |
| Average DC voltage across capacitance | 1.2 V; capacitive excitation |
| Shield driver capability | 400 pF; f = 25 kHz, SHLDn to GND, n = 1, 2 |
| Supply voltage | 3 V min, 3.3 V nominal, 3.6 V max; recommended operating conditions, VDD-GND |
| Operating temperature | -40 degC min, 125 degC max; recommended operating conditions |
| Supply current | 750 uA typ, 950 uA max; conversion mode; digital input to VDD or GND |
| Standby current | 29 uA typ, 70 uA max; standby; digital input to VDD or GND |
| Programmable output rates | 100 / 200 / 400 S/s; feature summary |
| Interface | I2C; MCU interface |
| I2C clock frequency | 10 kHz min, 400 kHz max; I2C interface timing |
| I2C input high voltage | 0.7 x VDD min; VDD = 3.3 V, TA = TJ = 25 degC unless otherwise noted |
| I2C input low voltage | 0.3 x VDD max; VDD = 3.3 V, TA = TJ = 25 degC unless otherwise noted |
| I2C output low voltage | 0.4 V max; sink current = 3 mA |
| I2C input hysteresis | 0.1 x VDD typ; specified by design and/or characterization, not tested in production |
| Clock low time | 1.3 us min; I2C interface timing |
| Clock high time | 0.6 us min; I2C interface timing |
| Repeated START hold time | 0.6 us min; after this period, first clock pulse is generated |
| Repeated START setup time | 0.6 us min; I2C interface timing |
| Data hold time | 0 ns min; FDC1004 provides internal 300 ns minimum hold time |
| Data setup time | 100 ns min; I2C interface timing |
| SDA fall time | 300 ns max; IL <= 3 mA; CL <= 400 pF |
| STOP condition setup time | 0.6 us min; I2C interface timing |
| Bus free time between STOP and START | 1.3 us min; I2C interface timing |
| Data valid time | 0.9 ns max; I2C interface timing |
| Data valid acknowledge time | 0.9 ns max; I2C interface timing |
| Input spike suppression pulse width | 50 ns max; I2C input filter |
| Absolute maximum VDD input voltage | -0.3 V min, 6 V max; absolute maximum ratings |
| Absolute maximum SCL/SDA input voltage | -0.3 V min, 6 V max; absolute maximum ratings |
| Absolute maximum voltage at any other pin | -0.3 V min, VDD + 0.3 V max; absolute maximum ratings |
| Input current at any pin | 3 mA max; absolute maximum ratings |
| Junction temperature | 150 degC max; absolute maximum ratings |
| Storage temperature | -65 degC min, 150 degC max; absolute maximum ratings |
| ESD rating, human body model | +/-1000 V; ANSI/ESDA/JEDEC JS-001, all pins |
| ESD rating, charged device model | +/-250 V; JEDEC JESD22-C101, all pins |
| Junction-to-ambient thermal resistance | 46.8 degC/W; WSON (DSC) 10 pins and VSSOP (DGS) 10 pins |
| Junction-to-case top thermal resistance | 46.7 degC/W WSON; 48.7 degC/W VSSOP; 10-pin packages |
| Junction-to-board thermal resistance | 21.5 degC/W WSON; 70.6 degC/W VSSOP; 10-pin packages |
| Datasheet Status | request_only |
Product Overview
The FDC1004 is a Texas Instruments Signal_Chain sensor component implemented as a 4-channel capacitance-to-digital converter. Its capacitive sensing inputs are CIN1 through CIN4, with a +/-15 pF full-scale input conversion range per channel and support for up to 100 pF maximum input offset capacitance per channel when the CINn series resistance is 0 ohm.
Measurement specifications include 0.5 fF resolution, 16-bit effective resolution at 100 S/s with no external capacitance connected, and 33.2 aF/sqrt(Hz) output noise under the same condition. Offset and gain parameters include +/-6 fF absolute error after offset calibration, 46 fF offset deviation over -40 degC to 125 degC, 0.2% gain error, and -37.5 ppm/degC gain drift.
The device supports 100, 200, and 400 S/s programmable output rates and communicates through I2C with a 10 kHz to 400 kHz clock range. It operates from a 3 V to 3.6 V supply and is available in 10-pin WSON and VSSOP packages.
Key Features
- Four capacitive sensing inputs, CIN1 through CIN4
- +/-15 pF input conversion range per channel
- 0.5 fF measurement resolution from feature summary
- 16-bit effective resolution at 100 S/s
- 33.2 aF/sqrt(Hz) output noise at 100 S/s
- 96.9 pF CAPDAC full-scale range
- 25 kHz capacitive excitation with 2.4 Vpp signal
- 400 pF shield driver capability at 25 kHz
- 3 V to 3.6 V recommended supply range
- I2C interface with 10 kHz to 400 kHz clock
Typical Applications
- Capacitive sensing input modules
- Four-channel capacitance measurement
- I2C-connected sensor interfaces
- Shielded capacitive sensor electrodes
- Low-current conversion-mode systems
- Wide-temperature sensing electronics
Procurement Notes
When requesting a quote for FDC1004, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
How many capacitive input channels does the FDC1004 provide?
The FDC1004 provides four capacitive sensing inputs, identified as CIN1 through CIN4. Each channel has a capacitive input full-scale conversion range of +/-15 pF.
What supply voltage range is recommended for FDC1004 operation?
The recommended VDD-to-GND supply range is 3 V minimum, 3.3 V nominal, and 3.6 V maximum. The specified operating temperature range is -40 degC to 125 degC.
What interface and output rates does the FDC1004 support?
The FDC1004 uses an I2C MCU interface. Its I2C clock frequency range is 10 kHz to 400 kHz, and the programmable output rates listed in the feature summary are 100, 200, and 400 S/s.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 20, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.