Specifications
| Type | Description |
|---|---|
| Part Number | LM5067 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Component Type | Power_IC |
| Package Case | VSSOP-10 3.00 mm x 3.00 mm; SOIC-14 8.99 mm x 7.49 mm |
| Operating input voltage range | -9 V to -80 V; Negative hot swap operation |
| Retry behavior LM5067-1 | Latch-off; After fault |
| Retry behavior LM5067-2 | Auto-retry; After fault |
| VCC-to-VEE operating voltage | 12.35 min, 13 typ, 13.65 max V; ICC=2 mA, UVLO=5 V |
| Internal operating current enabled | 0.8 typ, 1 max mA; VCC-VEE=11 V, UVLO=5 V |
| Internal operating current disabled | 480 typ, 660 max uA; VCC-VEE=11 V, UVLO=2 V |
| Insertion timer start threshold | 7.7 typ, 8.2 max V; VCC-VEE increasing |
| Enable-all-functions threshold | 8.4 typ, 8.7 max V; VCC-VEE increasing |
| Enable threshold hysteresis | 125 mV; VCC-VEE decreasing |
| OUT bias current enabled | 0.1 uA; OUT=VEE, normal operation |
| OUT bias current disabled | 50 uA; Disabled, OUT=VEE+48 V |
| SENSE bias current enabled | -6 uA; OUT=VEE, normal operation |
| SENSE bias current disabled | -50 uA; Disabled, OUT=VEE+48 V |
| UVLO threshold | 2.45 min, 2.5 typ, 2.55 max V; UVLO pin relative to VEE |
| UVLO hysteresis current | 10 min, 22 typ, 34 max uA; UVLO=VEE+2 V |
| UVLO bias current | 1 uA; UVLO=VEE+5 V |
| OVLO threshold | 2.43 min, 2.5 typ, 2.57 max V; OVLO pin relative to VEE |
| OVLO hysteresis current | -34 min, -22 typ, -10 max uA; OVLO=VEE+2.8 V |
| OVLO bias current | 1 uA; OVLO=VEE+2.4 V |
| GATE source current | -72 min, -52 typ, -32 max uA; Normal operation |
| GATE sink current UVLO | 1.9 min, 2.2 typ, 2.68 max mA; UVLO<2.5 V |
| GATE sink current fault | 45 min, 110 typ, 200 max mA; SENSE-VEE=150 mV or VCC-VEE<PORIT, VGATE=5 V |
| Gate output voltage normal operation | VZ V; GATE-VEE voltage |
| Current limit threshold | 44 min, 50 typ, 56 max mV; SENSE-VEE voltage |
| Circuit breaker threshold | 70 min, 100 typ, 130 max mV; SENSE-VEE voltage |
| Power limit sense voltage | 16.5 min, 22 typ, 27.5 max mV; OUT-SENSE=24 V, RPWR=75 kOhm |
| PWR pin current | -23 uA; VPWR=2.5 V |
| TIMER upper threshold | 3.76 min, 4 typ, 4.16 max V; TIMER pin |
| TIMER lower threshold restart cycles | 1.18 min, 1.25 typ, 1.32 max V; LM5067-2 restart cycles |
| TIMER lower threshold end of 8th cycle | 0.3 V; LM5067-2 |
| TIMER re-enable threshold | 0.3 V; LM5067-1 |
| Insertion time current | -9.5 min, -6 typ, -2.5 max uA; TIMER pin=2 V |
| TIMER sink current end of insertion time | 1.2 min, 1.55 typ, 1.9 max mA; TIMER pin=2 V |
| Fault detection current | -140 min, -95 typ, -44 max uA; TIMER pin=2 V |
| TIMER sink current end of fault time | 0.9 min, 2.5 typ, 4.25 max uA; End of fault time |
| Fault restart duty cycle | 0.5%; LM5067-2 |
| PGD falling threshold | 1.162 min, 1.23 typ, 1.285 max V; External MOSFET VDS decreasing |
| OUT and PGD absolute maximum voltage | -0.3 min, 100 max V; OUT, PGD to VEE |
| UVLO and OVLO absolute maximum voltage | -0.3 min, 17 max V; UVLO, OVLO to VEE |
| SENSE absolute maximum voltage | -0.3 min, 0.3 max V; SENSE to VEE |
| VCC pulse current absolute maximum | 100 mA; 100 us pulse into VCC |
| Junction temperature absolute maximum | 150 °C; Absolute maximum rating |
| Storage temperature | -65 min, 150 max °C; Absolute maximum rating |
| Recommended VCC current | 2 mA; Current into VCC |
| Recommended OUT voltage | 0 min, 80 max V; OUT voltage above VEE |
| Recommended PGD off voltage | 0 min, 80 max V; PGD off voltage above VEE |
| Recommended junction temperature | -40 min, 125 max °C; Operating free-air temperature range |
| HBM ESD rating LM50672NPA variant | ±1750 V; ANSI/ESDA/JEDEC JS-001, all pins |
| HBM ESD rating other variants | ±2000 V; ANSI/ESDA/JEDEC JS-001, all pins |
| CDM ESD rating | ±500 V; JEDEC JESD22-C101, all pins |
| Junction-to-ambient thermal resistance VSSOP-10 | 94 °C/W; 4-layer JEDEC board with 2 vias under package |
| Junction-to-ambient thermal resistance SOIC-14 | 90 °C/W; 4-layer JEDEC board with 2 vias under package |
| Junction-to-case thermal resistance VSSOP-10 | 44 °C/W; 4-layer JEDEC board with 2 vias under package |
| Junction-to-case thermal resistance SOIC-14 | 27 °C/W; 4-layer JEDEC board with 2 vias under package |
| Datasheet Status | request_only |
Product Overview
The LM5067 is a Texas Instruments negative hot swap controller for Power_Management designs operating from -9 V to -80 V input rails. It controls an external MOSFET through the GATE pin and provides thresholds for current limiting, circuit breaker action, power limiting, UVLO, OVLO, timer operation, and PGD indication.
Key Features
- -9 V to -80 V negative hot swap operation
- LM5067-1 latch-off behavior after fault
- LM5067-2 auto-retry behavior after fault
- 50 mV typical current limit threshold
- 100 mV typical circuit breaker threshold
- 2.5 V typical UVLO threshold
- 2.5 V typical OVLO threshold
- 110 mA typical GATE fault sink current
- 0.5% fault restart duty cycle for LM5067-2
- VSSOP-10 and SOIC-14 package options
Typical Applications
- Negative hot swap control
- -9 V to -80 V rails
- External MOSFET gate control
- Fault latch-off designs
- Auto-retry fault designs
- UVLO and OVLO monitoring
- Current limit protection
- Power-good drain monitoring
Procurement Notes
When requesting a quote for LM5067, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What input voltage range does the LM5067 support?
The LM5067 supports negative hot swap operation across an operating input voltage range of -9 V to -80 V, according to the extracted manufacturer datasheet facts.
How do LM5067-1 and LM5067-2 differ after faults?
The LM5067-1 uses latch-off behavior after a fault, while the LM5067-2 uses auto-retry behavior after a fault. The LM5067-2 fault restart duty cycle is specified as 0.5%.
Which packages are listed for the LM5067?
The extracted package data lists VSSOP-10 at 3.00 mm x 3.00 mm and SOIC-14 at 8.99 mm x 7.49 mm for the LM5067.
What current and circuit breaker thresholds are specified?
The LM5067 current limit threshold is 44 mV minimum, 50 mV typical, and 56 mV maximum. The circuit breaker threshold is 70 mV minimum, 100 mV typical, and 130 mV maximum.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 20, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.