Specifications
| Type | Description |
|---|---|
| Part Number | LMK00301 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | RHS WQFN-48, 7.00 mm × 7.00 mm |
| Input multiplexer | 3:1; two universal inputs plus one crystal input |
| Universal input maximum frequency | 3.1 GHz for CLKin0/CLKin1 universal inputs |
| Universal input supported formats | LVPECL, LVDS, CML, SSTL, HSTL, HCSL, single-ended clocks |
| Crystal input frequency range | 10 MHz to 40 MHz on OSCin crystal input |
| Differential output count | 10 outputs; two banks with five differential outputs each |
| LVCMOS output count | 1 REFout output |
| Differential output bank modes | LVPECL, LVDS, HCSL, Hi-Z; selectable per output bank |
| LVPECL frequency range | DC to 3100 MHz for differential outputs configured as LVPECL |
| LVDS frequency range | DC to 2100 MHz for differential outputs configured as LVDS |
| HCSL frequency range | DC to 800 MHz for differential outputs configured as HCSL |
| LVCMOS frequency range | DC to 250 MHz for REFout output |
| LVPECL additive RMS jitter | 20 fs RMS with LMK03806 clock source at 156.25 MHz, 10 kHz to 1 MHz |
| LVPECL additive RMS jitter | 51 fs RMS with LMK03806 clock source at 156.25 MHz, 12 kHz to 20 MHz |
| Additive RMS jitter after PCIe Gen 7 filters | 9.38 fs LVPECL, 10.1 fs HCSL, 12.6 fs LVDS maximum |
| Additive RMS jitter after PCIe Gen 6 filters | 13.4 fs LVPECL, 14.3 fs HCSL, 18.0 fs LVDS maximum |
| Additive RMS jitter after PCIe Gen 5 filters | 21.8 fs LVPECL, 23.6 fs HCSL, 30.3 fs LVDS maximum |
| PSRR | -65 dBc for LVPECL output at 156.25 MHz |
| PSRR | -76 dBc for LVDS output at 156.25 MHz |
| Core supply voltage | 3.3 V ±5% for VCC core supply |
| Output supply voltage | 3.3 V or 2.5 V ±5% for VCCOA, VCCOB, VCCOC output supplies |
| Operating ambient temperature | -40°C to +85°C industrial temperature range |
| Power sequencing requirement | Required for LMK00301; all core and output supplies ramp at the same time or must be tied together |
| Power sequencing requirement | Not required for LMK00301A design spin |
| Supply voltage absolute maximum | -0.3 V to 3.6 V for VCC, VCCO |
| Input voltage absolute maximum | -0.3 V to VCC + 0.3 V for VIN |
| Storage temperature | -65°C to +150°C for TSTG |
| Lead temperature | +260°C for soldering for 4 seconds |
| Junction temperature absolute maximum | +150°C for TJ |
| ESD HBM rating | ±2000 V, human-body model per ANSI/ESDA/JEDEC JS-001 |
| ESD machine model rating | ±150 V machine model |
| ESD CDM rating | ±750 V charged-device model per JEDEC JESD22C101 |
| Recommended ambient temperature | min -40°C, typ 25°C, max 85°C for TA operating free-air temperature range |
| Recommended junction temperature | max 125°C for TJ |
| Recommended core supply voltage | min 3.15 V, typ 3.3 V, max 3.45 V for VCC |
| Recommended 3.3 V output supply voltage | min 3.3 V -5%, typ 3.3 V, max 3.3 V +5% for VCCO |
| Recommended 2.5 V output supply voltage | min 2.5 V -5%, typ 2.5 V, max 2.5 V +5% for VCCO |
| Output supply constraint | VCCO ≤ VCC for any output bank |
| Junction-to-ambient thermal resistance | 28.5 °C/W for RHS0048A WQFN-48, JEDEC 4-layer board with 16 thermal vias |
| Junction-to-case top thermal resistance | 7.2 °C/W for RHS0048A WQFN-48, DAP |
| Datasheet Status | request_only |
Product Overview
The LMK00301 is a Texas Instruments differential clock buffer translator for Signal_Chain clock distribution. Its input structure uses a 3:1 multiplexer with two CLKin0/CLKin1 universal inputs and one OSCin crystal input. The universal inputs operate up to 3.1 GHz and support LVPECL, LVDS, CML, SSTL, HSTL, HCSL, and single-ended clock formats, while the crystal input supports 10 MHz to 40 MHz operation.
The output structure provides ten differential outputs arranged as two banks with five differential outputs each, plus one REFout LVCMOS output. Each differential output bank can be selected for LVPECL, LVDS, HCSL, or Hi-Z operation. Frequency coverage is DC to 3100 MHz for LVPECL, DC to 2100 MHz for LVDS, DC to 800 MHz for HCSL, and DC to 250 MHz for the LVCMOS REFout output.
The device uses a 3.3 V ±5% core supply, with output supplies at 3.3 V or 2.5 V ±5% and VCCO constrained to be no greater than VCC. It is specified for -40°C to +85°C ambient operation in an RHS WQFN-48, 7.00 mm × 7.00 mm package. For LMK00301, supply ramping requires all core and output supplies to ramp at the same time or be tied together; the LMK00301A design spin does not require this sequencing.
Key Features
- 3:1 input multiplexer with two universal inputs
- Universal inputs support clock formats up to 3.1 GHz
- OSCin crystal input supports 10 MHz to 40 MHz
- Ten differential outputs across two five-output banks
- One REFout LVCMOS output supports DC to 250 MHz
- Selectable LVPECL, LVDS, HCSL, or Hi-Z bank modes
- LVPECL differential outputs support DC to 3100 MHz
- LVDS differential outputs support DC to 2100 MHz
- HCSL differential outputs support DC to 800 MHz
- Industrial -40°C to +85°C ambient operation
- 3.3 V core supply with 2.5 V or 3.3 V outputs
- RHS WQFN-48 package with 7.2 °C/W top case resistance
Typical Applications
- PCIe Gen 5 clock distribution
- PCIe Gen 6 clock distribution
- PCIe Gen 7 clock distribution
- 156.25 MHz clock buffering
- LVPECL clock translation
- LVDS clock translation
- HCSL clock fanout
- LVCMOS reference clock output
- Crystal-referenced clock distribution
Procurement Notes
When requesting a quote for LMK00301, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What input options does the LMK00301 provide?
The LMK00301 uses a 3:1 input multiplexer with two CLKin0/CLKin1 universal inputs and one OSCin crystal input. The universal inputs support LVPECL, LVDS, CML, SSTL, HSTL, HCSL, and single-ended clock formats up to 3.1 GHz.
How many outputs are available on the LMK00301?
The device provides ten differential outputs arranged as two banks with five differential outputs each. It also includes one REFout LVCMOS output, specified for DC to 250 MHz operation.
Which differential output formats are selectable by bank?
Each differential output bank can be configured for LVPECL, LVDS, HCSL, or Hi-Z operation. The supported frequency ranges are DC to 3100 MHz for LVPECL, DC to 2100 MHz for LVDS, and DC to 800 MHz for HCSL.
What supply voltages are recommended for this device?
The recommended core supply is 3.15 V minimum, 3.3 V typical, and 3.45 V maximum. Output supplies can use 3.3 V ±5% or 2.5 V ±5%, with the constraint that VCCO must be less than or equal to VCC.
Does the LMK00301 require power supply sequencing?
For LMK00301, power sequencing is required: all core and output supplies must ramp at the same time or be tied together. The LMK00301A design spin is listed as not requiring this sequencing.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 7, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.