LMK00304 Differential Clock Buffer/Level Translator

Texas Instruments Signal_Chain — specifications, applications, sourcing support and RFQ.

LMK00304 Differential Clock Buffer/Level Translator

RFQ Available Sourcing Support Alternative Matching RoHS
Part Number
LMK00304
Manufacturer
Texas Instruments
Package
32-lead WQFN (RTV0032A), 5.00 mm x 5.00 mm body
Category
Signal Chain
Product Type
Operational Amplifier

Quick Sourcing Note

LMK00304 from Texas Instruments is a Signal_Chain differential clock buffer/level translator supplied in a 32-lead WQFN (RTV0032A), 5.00 mm x 5.00 mm body. It provides four differential outputs arranged as two banks, a 3:1 input multiplexer, two universal inputs up to 3.1 GHz, and a 10 MHz to 40 MHz crystal input. The device supports LVPECL, LVDS, CML, SSTL, HSTL, HCSL, and single-ended input clocks, with selectable LVPECL, LVDS, HCSL, or Hi-Z differential outputs. Key use cases include differential clock buffering, level translation, reference clock fanout, crystal-input clock distribution, and LVCMOS reference output generation.

Specifications

TypeDescription
Part NumberLMK00304
ManufacturerTexas Instruments
Product TypeOperational Amplifier
CategorySignal Chain
Package Case32-lead WQFN (RTV0032A), 5.00 mm x 5.00 mm body
Number of Differential Outputs4 outputs arranged as two banks with 2 differential outputs each; Bank A and Bank B
Input Multiplexer3:1 input multiplexer; two universal inputs plus one crystal input
Universal Input FrequencyUp to 3.1 GHz; universal inputs CLKin0/CLKin0* and CLKin1/CLKin1*
Universal Input Supported FormatsLVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks
Crystal Input Frequency10 MHz to 40 MHz; also accepts single-ended clock
Differential Output FormatsLVPECL, LVDS, HCSL, or Hi-Z; selectable by CLKout_TYPE pins
LVCMOS Reference Output1 output; REFout with synchronous enable input
LVPECL Additive RMS Jitter20 fs RMS; LMK03806 clock source at 156.25 MHz, integration bandwidth 10 kHz to 1 MHz
LVPECL Additive RMS Jitter51 fs RMS; LMK03806 clock source at 156.25 MHz, integration bandwidth 12 kHz to 20 MHz
PSRR-65 dBc; LVPECL output at 156.25 MHz
PSRR-76 dBc; LVDS output at 156.25 MHz
Core Supply Voltage3.3 V ±5%; VCC core supply
Output Supply Voltage3.3 V or 2.5 V ±5%; VCCOA, VCCOB, VCCOC independent output supplies
Ambient Temperature Range-40°C to +85°C; industrial operating range
PackageWQFN-32, 5 mm x 5 mm
Absolute Maximum Supply Voltage-0.3 V to 3.6 V; VCC and VCCO over operating free-air temperature range
Absolute Maximum Input Voltage-0.3 V to VCC + 0.3 V; VIN over operating free-air temperature range
Storage Temperature Range-65°C to +150°C; TSTG absolute maximum rating
Lead Temperature+260°C; soldering for 4 seconds
Junction Temperature Absolute Maximum+150°C; TJ absolute maximum rating
ESD Rating HBM±2000 V; human-body model per ANSI/ESDA/JEDEC JS-001
ESD Rating MM±150 V; machine model
ESD Rating CDM±750 V; charged-device model per JEDEC JESD22-C101
Recommended Ambient TemperatureMin -40°C, Typ 25°C, Max 85°C; TA recommended operating condition
Recommended Junction TemperatureMax 125°C; TJ recommended operating condition
Recommended Core Supply VoltageMin 3.15 V, Typ 3.3 V, Max 3.45 V; VCC recommended operating condition
Recommended Output Supply VoltageMin 3.135 V, Typ 3.3 V, Max 3.465 V; VCCO = 3.3 V nominal output supply
Recommended Output Supply VoltageMin 2.375 V, Typ 2.5 V, Max 2.625 V; VCCO = 2.5 V nominal output supply
Output Supply ConstraintVCCO ≤ VCC; any output bank supply
Junction-to-Ambient Thermal Resistance38.1°C/W; RTV0032A WQFN, 32 pins
Junction-to-Case Top Thermal Resistance7.2°C/W; RTV0032A WQFN, 32 pins
VCCOA PinsPins 2 and 5; Bank A output buffer power supply, internally tied together
VCCOB PinsPins 20 and 23; Bank B output buffer power supply, internally tied together
VCCOC PinPin 30; REFout buffer power supply
Core VCC PinsPins 10 and 28; core and input buffer power supply
Control Input BiasingInternal pull-down resistor; CLKout_TYPE0/1, CLKin_SEL0/1, REFout_EN CMOS control inputs
Datasheet Statusrequest_only

Product Overview

The Texas Instruments LMK00304 is a differential clock buffer/level translator for Signal_Chain clock distribution paths. It includes four differential outputs organized as two banks with two differential outputs each, plus one LVCMOS REFout output with a synchronous enable input.

Input selection is handled by a 3:1 input multiplexer using two universal inputs and one crystal input. The universal CLKin0/CLKin0* and CLKin1/CLKin1* inputs support operation up to 3.1 GHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks. The crystal input supports 10 MHz to 40 MHz and also accepts a single-ended clock.

Output formats are selectable through the CLKout_TYPE pins and include LVPECL, LVDS, HCSL, or Hi-Z. The device uses a 3.3 V ±5% core supply and independent 3.3 V or 2.5 V ±5% output supplies with VCCO constrained to be no greater than VCC. It is specified for -40°C to +85°C ambient operation in a WQFN-32, 5 mm x 5 mm package.

Key Features

  • Four differential outputs in two output banks
  • 3:1 input multiplexer with crystal input path
  • Universal inputs support up to 3.1 GHz
  • Universal inputs accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL
  • Crystal input supports 10 MHz to 40 MHz
  • Selectable LVPECL, LVDS, HCSL, or Hi-Z outputs
  • One LVCMOS REFout with synchronous enable
  • 20 fs RMS LVPECL additive jitter over 10 kHz to 1 MHz
  • Independent 3.3 V or 2.5 V output supplies
  • WQFN-32 package with 5 mm x 5 mm body

Typical Applications

  • Differential clock buffering
  • Clock level translation
  • Reference clock fanout
  • Crystal-input clock distribution
  • LVCMOS reference output generation
  • LVPECL output clock distribution
  • LVDS output clock distribution
  • HCSL output clock distribution

Procurement Notes

When requesting a quote for LMK00304, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.

If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.

For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.

FAQ

How many differential outputs does the LMK00304 provide?

The LMK00304 provides four differential outputs. They are arranged as two output banks, Bank A and Bank B, with two differential outputs in each bank.

What input clock formats are supported by the universal inputs?

The universal inputs support LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks. These inputs are CLKin0/CLKin0* and CLKin1/CLKin1* and support frequencies up to 3.1 GHz.

What supply voltages are used by the LMK00304?

The core VCC supply is 3.3 V ±5%. The independent output supplies VCCOA, VCCOB, and VCCOC may use 3.3 V or 2.5 V ±5%, with the constraint that VCCO must not exceed VCC.

What package and temperature range apply to this device?

The LMK00304 is supplied in a WQFN-32, 5 mm x 5 mm package. Its industrial ambient operating range is -40°C to +85°C, with recommended junction temperature specified up to 125°C.

Technical Review & Sourcing Note

Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 7, 2026.

This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.

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