LMK00306 Differential Clock Buffer Level Translator

Texas Instruments Signal_Chain — specifications, applications, sourcing support and RFQ.

LMK00306 Differential Clock Buffer Level Translator

RFQ Available Sourcing Support Alternative Matching RoHS
Part Number
LMK00306
Manufacturer
Texas Instruments
Package
36-lead WQFN, 6.00 mm x 6.00 mm body size, package NJK0036A
Category
Signal Chain
Product Type
Operational Amplifier

Quick Sourcing Note

LMK00306 from Texas Instruments is a Signal_Chain differential clock buffer/level translator in a 36-lead WQFN package with a 6.00 mm x 6.00 mm body size. It provides six differential outputs arranged as two banks with three outputs each, plus one LVCMOS REFout. The 3:1 input multiplexer selects from two universal inputs or one crystal input. Universal inputs support LVPECL, LVDS, CML, SSTL, HSTL, HCSL, and single-ended clocks up to 3.1 GHz, while the crystal input range is 10 MHz to 40 MHz. Output banks support LVPECL, LVDS, HCSL, or Hi-Z operation across the -40°C to +85°C ambient range.

Specifications

TypeDescription
Part NumberLMK00306
ManufacturerTexas Instruments
Product TypeOperational Amplifier
CategorySignal Chain
Package Case36-lead WQFN, 6.00 mm x 6.00 mm body size, package NJK0036A
Number of Differential Outputs6 outputs; two banks with 3 differential outputs each
Input Multiplexer3:1; selectable from two universal inputs or one crystal input
Universal Input Maximum Frequency3.1 GHz for CLKin0/CLKin0* and CLKin1/CLKin1* universal inputs
Supported Universal Input TypesLVPECL, LVDS, CML, SSTL, HSTL, HCSL, single-ended clocks
Crystal Input Frequency Range10 MHz to 40 MHz for crystal input or single-ended clock input
Differential Output TypesLVPECL, LVDS, HCSL, or Hi-Z; selectable per output bank
LVCMOS Output1 REFout; reference output with synchronous enable input
LVPECL Additive RMS Jitter, 10 kHz to 1 MHz20 fs RMS with LMK03806 clock source at 156.25 MHz
LVPECL Additive RMS Jitter, 12 kHz to 20 MHz51 fs RMS with LMK03806 clock source at 156.25 MHz
Power Supply Rejection Ratio, LVPECL-65 dBc at 156.25 MHz output
Power Supply Rejection Ratio, LVDS-76 dBc at 156.25 MHz output
Core Supply Voltage3.3 V ±5% for VCC core supply
Output Supply Voltage3.3 V or 2.5 V ±5% for VCCOA, VCCOB, VCCOC independent output supplies
Number of Independent Output Supplies3; VCCOA, VCCOB, VCCOC
Operating Ambient Temperature-40°C to +85°C industrial temperature range
PackageWQFN-36
Package Body Size6.00 mm x 6.00 mm
Absolute Maximum Supply Voltage-0.3 V to 3.6 V for VCC and VCCO over operating free-air temperature range
Absolute Maximum Input Voltage-0.3 V to VCC + 0.3 V for VIN over operating free-air temperature range
Storage Temperature-65°C to +150°C absolute maximum rating
Lead Temperature+260°C for soldering for 4 seconds
Maximum Junction Temperature+150°C absolute maximum rating
ESD Rating HBM±2000 V per ANSI/ESDA/JEDEC JS-001
ESD Rating Machine Model±150 V
ESD Rating CDM±750 V per JEDEC JESD22-C101
Recommended Ambient TemperatureMin -40°C, Typ 25°C, Max 85°C
Recommended Junction TemperatureMax 125°C
Recommended Core Supply VoltageMin 3.15 V, Typ 3.3 V, Max 3.45 V
Recommended Output Supply Voltage, 3.3 V VCCOMin 3.135 V, Typ 3.3 V, Max 3.465 V
Recommended Output Supply Voltage, 2.5 V VCCOMin 2.375 V, Typ 2.5 V, Max 2.625 V
Output Supply ConstraintVCCO ≤ VCC
Clock Input Selection PinsCLKin_SEL0, CLKin_SEL1; CMOS control inputs with internal pull-down resistor
Output Type Selection PinsCLKoutA_TYPE0/1 and CLKoutB_TYPE0/1; CMOS control inputs with internal pull-down resistor
REFout Enable InputREFout_EN; enable signal internally synchronized to selected clock input; CMOS control input with internal pull-down resistor
Datasheet Statusrequest_only

Product Overview

The LMK00306 is a Texas Instruments differential clock buffer/level translator for Signal_Chain designs requiring format-compatible clock distribution. Its input structure uses a 3:1 multiplexer selectable from two universal inputs or one crystal input. The universal inputs accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, and single-ended clocks up to 3.1 GHz, while the crystal or single-ended input range is 10 MHz to 40 MHz.

The output structure provides six differential outputs organized as two banks with three outputs per bank. Differential output types are selectable per bank as LVPECL, LVDS, HCSL, or Hi-Z. The device also includes one LVCMOS REFout with a synchronous enable input, REFout_EN, internally synchronized to the selected clock input.

The device uses a 36-lead WQFN package, package NJK0036A, with a 6.00 mm x 6.00 mm body size. Recommended supplies are 3.15 V to 3.45 V for VCC, 3.135 V to 3.465 V for 3.3 V VCCO, or 2.375 V to 2.625 V for 2.5 V VCCO, with VCCO constrained to be no greater than VCC. Assembly-related limits include +260°C lead temperature for 4 seconds.

Key Features

  • Six differential outputs in two three-output banks
  • 3:1 input multiplexer for universal or crystal inputs
  • Universal inputs support clocks up to 3.1 GHz
  • Supports LVPECL, LVDS, CML, SSTL, HSTL, HCSL inputs
  • Crystal input range from 10 MHz to 40 MHz
  • Output banks selectable as LVPECL, LVDS, HCSL, or Hi-Z
  • One LVCMOS REFout with synchronous enable input
  • 20 fs RMS LVPECL additive jitter at 156.25 MHz
  • Three independent output supplies: VCCOA, VCCOB, VCCOC
  • Industrial ambient operating range from -40°C to +85°C

Typical Applications

  • Differential clock distribution
  • Clock level translation
  • LVPECL clock fanout
  • LVDS clock fanout
  • HCSL clock fanout
  • Crystal-referenced clock paths
  • Reference clock output distribution
  • Industrial-temperature signal-chain systems

Procurement Notes

When requesting a quote for LMK00306, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.

If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.

For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.

FAQ

How many differential outputs does the LMK00306 provide?

The LMK00306 provides six differential outputs. The outputs are arranged as two banks, with three differential outputs in each bank, and the differential output type is selectable per output bank.

What input clock formats are supported by LMK00306?

The universal clock inputs support LVPECL, LVDS, CML, SSTL, HSTL, HCSL, and single-ended clocks. The universal input maximum frequency is 3.1 GHz for CLKin0/CLKin0* and CLKin1/CLKin1*.

What supply voltages are recommended for this device?

The recommended core supply is 3.15 V to 3.45 V with 3.3 V typical. Output supplies may use 3.135 V to 3.465 V for 3.3 V operation or 2.375 V to 2.625 V for 2.5 V operation, with VCCO no greater than VCC.

What package is used for the LMK00306?

The LMK00306 is specified in a WQFN-36 package. The package case is a 36-lead WQFN with a 6.00 mm x 6.00 mm body size, identified as package NJK0036A.

Technical Review & Sourcing Note

Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 7, 2026.

This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.

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