LMK03806 Ultra Low Jitter Clock Generator

Texas Instruments Signal_Chain — specifications, applications, sourcing support and RFQ.

LMK03806 Ultra Low Jitter Clock Generator

RFQ Available Sourcing Support Alternative Matching RoHS
Part Number
LMK03806
Manufacturer
Texas Instruments
Package
64-pin WQFN (NKD), 9.00 mm x 9.00 mm
Category
Signal Chain
Product Type
Operational Amplifier

Quick Sourcing Note

LMK03806 from Texas Instruments is a Signal_Chain ultra low jitter clock generator supplied in a 64-pin WQFN (NKD), 9.00 mm x 9.00 mm package. It provides 14 programmable outputs with LVDS, LVPECL, or LVCMOS output format support, up to 8 unique output frequencies, and clock output synthesis up to 2.6 GHz. The tunable VCO range is 2.37 GHz to 2.6 GHz. Jitter is specified below 50 fs from 1.875 MHz to 20 MHz and below 150 fs from 12 kHz to 20 MHz at 312.5 MHz output. The device operates from a 3.3 V nominal supply and supports crystal, XO, TCXO, or AC-coupled external clock references.

Specifications

TypeDescription
Part NumberLMK03806
ManufacturerTexas Instruments
Product TypeOperational Amplifier
CategorySignal Chain
Component TypeOther
Package / Case64-pin WQFN (NKD), 9.00 mm x 9.00 mm
Output clock count14 programmable outputs; programmable LVDS, LVPECL, or LVCMOS output format
Unique output frequenciesUp to 8 across programmable outputs
Maximum output frequencyUp to 2.6 GHz clock output synthesis capability
VCO frequency range2.37 GHz to 2.6 GHz tunable VCO frequency
RMS jitter, 1.875 MHz to 20 MHz< 50 fs at 312.5 MHz output frequency
RMS jitter, 12 kHz to 20 MHz< 150 fs at 312.5 MHz output frequency
Supply voltage3.15 V min, 3.3 V nom, 3.45 V max; recommended operating conditions
Ambient operating temperature-40 C min, 25 C nom, 85 C max at VCC = 3.3 V
Junction operating temperature125 C max at VCC = 3.3 V
Absolute maximum supply voltage-0.3 V min, 3.6 V max; never exceed 3.6 V
Absolute maximum input voltage-0.3 V to VCC + 0.3 V on input pins
Lead temperature260 C max for soldering, 4 seconds
Absolute maximum junction temperature150 C max
Differential input current-5 mA min, 5 mA max on OSCin/OSCin* differential input
Storage temperature-65 C min, 150 C max
Moisture sensitivity levelMSL 3 package handling rating
HBM ESD rating+/-2000 V per ANSI/ESDA/JEDEC JS-001
CDM ESD rating+/-750 V per JEDEC JESD22-C101
Machine model ESD rating+/-150 V
Junction-to-ambient thermal resistance25.2 C/W on 4-layer JEDEC PCB with 32 thermal vias from die attach pad to embedded copper plane
Junction-to-case top thermal resistance6.9 C/W; case defined as DAP die attach pad
Junction-to-board thermal resistance4.0 C/W for NKD 64-pin WQFN package
Junction-to-top characterization parameter0.1 C/W for NKD 64-pin WQFN package
Junction-to-board characterization parameter4.0 C/W for NKD 64-pin WQFN package
Junction-to-case bottom thermal resistance0.8 C/W for NKD 64-pin WQFN package
Powerdown supply current1 mA typ with no DC path to ground on OSCout1/1*
Supply current with all clocks enabled445 mA typ; CLKoutX_Y_DIV = 16, CLKoutX_TYPE = 1 (LVDS), PLL locked
PLL reference input frequency1 MHz min, 500 MHz max for external clock on OSCin
OSCin minimum slew rate0.15 V/ns min, 0.5 V/ns typ; 20% to 80% PLL reference clock slew rate on OSCin
OSCin single-ended input voltage0.2 Vpp min, 2.4 Vpp max; AC coupled, unused pin AC coupled to GND
OSCin differential input voltage0.2 V min, 1.55 V max; AC coupled differential voltage swing, VID
OSCin differential voltage swing0.4 Vpp min, 3.1 Vpp max; AC coupled, VSS
OSCin input offset voltage20 mV max DC offset between OSCin and OSCin*, each pin AC coupled
Doubler input frequency155 MHz max; EN_PLL_REF_2X = 1, OSCin duty cycle 40% to 60%
Crystal frequency range, low ESR16 MHz min, 20.5 MHz max; RESR <= 40 ohm, CL <= 20 pF
Crystal frequency range, higher ESR6 MHz min, 16 MHz max; RESR <= 80 ohm, CL <= 22 pF
Crystal power dissipation120 uW typ with Vectron VXB1 crystal, 20.48 MHz, RESR <= 40 ohm, CL <= 20 pF
Reference input typeCrystal, XO, TCXO, or external clock; external clock must be AC coupled
Programming interfaceMICROWIRE through CLKuWire, DATAuWire, and LEuWire CMOS inputs
Datasheet Statusrequest_only

Product Overview

The LMK03806 is a Texas Instruments Signal_Chain ultra low jitter clock generator for multi-output clock synthesis. It supports 14 programmable outputs using LVDS, LVPECL, or LVCMOS formats and can generate up to 8 unique output frequencies across those outputs. Its clock output synthesis capability extends up to 2.6 GHz, with a tunable VCO frequency range from 2.37 GHz to 2.6 GHz.

Clock performance is specified with RMS jitter below 50 fs over a 1.875 MHz to 20 MHz integration bandwidth and below 150 fs over a 12 kHz to 20 MHz integration bandwidth, both at 312.5 MHz output frequency. Reference input options include crystal, XO, TCXO, or an AC-coupled external clock through OSCin/OSCin*. Programming is through the MICROWIRE interface using CLKuWire, DATAuWire, and LEuWire CMOS inputs.

The device is housed in a 64-pin WQFN (NKD), 9.00 mm x 9.00 mm package. Recommended operation is from 3.15 V to 3.45 V, with -40 C to 85 C ambient operation and 125 C maximum junction operating temperature. Package handling and assembly facts include MSL 3, 260 C maximum lead temperature for 4 seconds, and thermal resistance values defined for the NKD WQFN package.

Key Features

  • 14 programmable clock outputs
  • LVDS, LVPECL, or LVCMOS output formats
  • Up to 8 unique output frequencies
  • Clock output synthesis up to 2.6 GHz
  • 2.37 GHz to 2.6 GHz tunable VCO
  • < 50 fs RMS jitter at 312.5 MHz
  • < 150 fs RMS jitter at 312.5 MHz
  • Crystal, XO, TCXO, or external clock reference
  • MICROWIRE programming interface with CMOS inputs
  • 64-pin WQFN package, 9.00 mm x 9.00 mm

Typical Applications

  • Multi-output clock generation
  • Low-jitter clock synthesis
  • LVDS clock distribution
  • LVPECL clock distribution
  • LVCMOS clock output systems
  • Crystal-referenced clock generation
  • XO or TCXO referenced designs
  • External reference clock systems

Procurement Notes

When requesting a quote for LMK03806, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.

If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.

For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.

FAQ

What type of device is the LMK03806?

The LMK03806 is an ultra low jitter clock generator from Texas Instruments in the Signal_Chain category. It provides 14 programmable outputs and supports LVDS, LVPECL, or LVCMOS output formats.

How many output frequencies can the LMK03806 generate?

The LMK03806 supports up to 8 unique output frequencies across its programmable outputs. Its clock output synthesis capability extends up to 2.6 GHz, with a tunable VCO range from 2.37 GHz to 2.6 GHz.

What reference inputs are supported by the LMK03806?

The LMK03806 reference input can use a crystal, XO, TCXO, or external clock through OSCin/OSCin*. The extracted datasheet facts specify that an external clock reference must be AC coupled.

What package is used for the LMK03806?

The LMK03806 is supplied in a 64-pin WQFN package, Texas Instruments package code NKD. The package body size is listed as 9.00 mm x 9.00 mm.

Technical Review & Sourcing Note

Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.

This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.

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