Specifications
| Type | Description |
|---|---|
| Part Number | LMK04828 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 64-pin QFN, 9.0 mm x 9.0 mm x 0.8 mm |
| JESD204B Support | Supported; JEDEC JESD204B compliant clocking |
| RMS Jitter | 88 fs RMS; 12 kHz to 20 MHz integration bandwidth |
| RMS Jitter | 91 fs RMS; 100 Hz to 20 MHz integration bandwidth |
| Noise Floor | -162.5 dBc/Hz; 245.76 MHz output |
| Device Clock Outputs | Up to 14 differential outputs; from PLL2 |
| SYSREF Clock Outputs | Up to 7 outputs; SYSREF clocks from PLL2 output paths |
| Maximum Clock Output Frequency | 3.1 GHz; clock outputs |
| PLL2 Output Formats | LVPECL, LVDS, HSDS, LCPECL; programmable outputs from PLL2 |
| Buffered VCXO/Crystal Output | Up to 1 output; from PLL1 |
| PLL1 Output Formats | LVPECL, LVDS, 2x LVCMOS; programmable buffered VCXO/crystal output |
| PLL Architecture | Dual-loop PLLatinum PLL; integrated clock conditioner architecture |
| Reference Input Clocks | Up to 3 redundant input clocks; PLL1 |
| Input Clock Switching | Automatic and manual switch-over modes; PLL1 redundant input clocks |
| Input Clock Protection | Hitless switching and LOS; PLL1 reference clock inputs |
| Holdover Mode | Supported; when input clocks are lost |
| PLL2 Normalized Noise Floor | -227 dBc/Hz; 1 Hz normalized PLL noise floor |
| PLL2 Phase Detector Rate | Up to 155 MHz; PLL2 |
| OSCin Frequency Doubler | Supported; PLL2 input path |
| Integrated VCO Count | 2; PLL2 integrated low-noise VCOs |
| LMK04828 VCO0 Frequency | 2370 MHz to 2630 MHz; device information table |
| LMK04828 VCO1 Frequency | 2920 MHz to 3080 MHz; device information table |
| Output Divider Range | 1 to 32; 50% duty-cycle output divides, even and odd |
| Analog Delay Step | 25 ps; precision analog delay |
| Functional Modes | Dual PLL, single PLL, clock distribution; multi-mode operation |
| Operating Temperature Range | -40°C to 85°C; industrial temperature range |
| Supported PCB Temperature | 105°C; measured at thermal pad |
| Supply Voltage | 3.15 V to 3.45 V; device operation |
| Datasheet Status | request_only |
Product Overview
The LMK04828 is a Texas Instruments clock jitter cleaner for Signal_Chain systems requiring JESD204B-compliant clocking. Its integrated clock conditioner architecture is a dual-loop PLLatinum PLL, with functional modes for dual PLL, single PLL, and clock distribution operation.
From PLL2, the device provides up to 14 differential device clock outputs and up to 7 SYSREF clock outputs. Clock outputs can run up to 3.1 GHz and support programmable LVPECL, LVDS, HSDS, and LCPECL formats. PLL2 also includes two integrated low-noise VCOs, with VCO0 covering 2370 MHz to 2630 MHz and VCO1 covering 2920 MHz to 3080 MHz.
PLL1 supports up to 3 redundant input clocks with automatic and manual switch-over modes, hitless switching, loss-of-signal protection, and holdover when input clocks are lost. The device is supplied in a 64-pin QFN package, operates from 3.15 V to 3.45 V, supports -40°C to 85°C operation, and allows 105°C PCB temperature measured at the thermal pad.
Key Features
- JESD204B-compliant clocking support
- 88 fs RMS jitter over 12 kHz to 20 MHz
- 91 fs RMS jitter over 100 Hz to 20 MHz
- Up to 14 PLL2 differential device clock outputs
- Up to 7 SYSREF outputs from PLL2 paths
- Clock output frequency up to 3.1 GHz
- PLL2 supports LVPECL, LVDS, HSDS, and LCPECL
- PLL1 supports redundant input clocks with hitless switching
- Holdover mode supported when input clocks are lost
- Dual PLL, single PLL, and clock distribution modes
Typical Applications
- JESD204B-compliant clocking
- Low-jitter clock conditioning
- SYSREF clock generation
- Differential clock distribution
- Redundant reference clock systems
- Dual PLL clock architectures
- Single PLL clock architectures
- Holdover clock operation
Procurement Notes
When requesting a quote for LMK04828, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the LMK04828?
The LMK04828 is a Texas Instruments clock jitter cleaner in the Signal_Chain category. It uses a dual-loop PLLatinum PLL architecture and supports dual PLL, single PLL, and clock distribution modes.
How many device and SYSREF outputs does LMK04828 support?
From PLL2, the LMK04828 supports up to 14 differential device clock outputs and up to 7 SYSREF clock outputs through the PLL2 output paths.
What jitter performance is specified for the LMK04828?
The extracted datasheet facts specify 88 fs RMS jitter over a 12 kHz to 20 MHz integration bandwidth and 91 fs RMS jitter over a 100 Hz to 20 MHz integration bandwidth.
What reference input protection functions are included?
PLL1 supports up to 3 redundant input clocks with automatic and manual switch-over modes. The extracted facts also specify hitless switching, LOS protection, and holdover mode when input clocks are lost.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.