Specifications
| Type | Description |
|---|---|
| Part Number | LMK1C1104 |
| Manufacturer | Texas Instruments |
| Product Type | LVCMOS Clock Buffer |
| Category | Signal Chain |
| Package / Case | 8-pin TSSOP, 3.00 mm x 4.40 mm; 8-pin WSON, 2.00 mm x 2.00 mm |
| Number of Outputs | 4; condition: LMK1C1104 device variant |
| Clock Buffer Fanout | 1:4; condition: LMK1C1104 |
| Logic Family | LVCMOS input and LVCMOS outputs; condition: functional block diagram and pin descriptions |
| Supply Voltage | 1.8 V, 2.5 V, or 3.3 V; condition: supported operating environments |
| 3.3 V Supply Voltage Range | 3.135 V min, 3.3 V nominal, 3.465 V max; condition: recommended operating conditions |
| 2.5 V Supply Voltage Range | 2.375 V min, 2.5 V nominal, 2.625 V max; condition: recommended operating conditions |
| 1.8 V Supply Voltage Range | 1.71 V min, 1.8 V nominal, 1.89 V max; condition: recommended operating conditions |
| Operating Free-Air Temperature | -40°C to 125°C; condition: recommended operating conditions |
| Operating Junction Temperature | -40°C to 150°C; condition: recommended operating conditions |
| Input Frequency | DC to 250 MHz; condition: VDD = 3.3 V |
| Input Frequency | DC to 200 MHz; condition: VDD = 2.5 V or 1.8 V |
| Output Frequency | 250 MHz max; condition: VDD = 3.3 V |
| Output Frequency | 200 MHz max; condition: VDD = 2.5 V or 1.8 V |
| Input High Voltage | 0.7 x VDD min; condition: clock input |
| Input Low Voltage | 0.3 x VDD max; condition: clock input |
| Input Slew Rate | 0.1 V/ns min; condition: 20% to 80% of input swing |
| Input Leakage Current | -50 uA min, 50 uA max; condition: clock input |
| Input Capacitance | 7 pF typical; condition: TA = 25°C |
| Static Core Supply Current | 25 uA typical, 45 uA max; condition: all outputs disabled, fIN = 0 V |
| Core Supply Current | 8 mA typical, 15 mA max; condition: all outputs disabled, fIN = 100 MHz |
| Core Supply Current | 14 mA typical, 20 mA max; condition: all outputs active, fIN = 100 MHz, CL = 5 pF, VDD = 1.8 V |
| Core Supply Current | 21 mA typical, 30 mA max; condition: all outputs active, fIN = 100 MHz, CL = 5 pF, VDD = 2.5 V |
| Core Supply Current | 33 mA typical, 40 mA max; condition: all outputs active, fIN = 100 MHz, CL = 5 pF, VDD = 3.3 V |
| Output Duty Cycle | 45% min, 55% max; condition: 50% duty cycle input, all VDD levels |
| Start-Up Time Before Output Active | 3 ms max; condition: clock output, all VDD levels |
| Output Enable Time | 5 cycles max; condition: 1G_ON |
| Output Disable Time | 5 cycles max; condition: 1G_OFF |
| Output High Voltage | 2.8 V min; condition: VDD = 3.3 V ±5%, IOH = 1 mA |
| Output Low Voltage | 0.2 V max; condition: VDD = 3.3 V ±5%, IOL = 1 mA |
| Output Rise and Fall Time | 0.35 ns typical, 0.7 ns max; condition: VDD = 3.3 V ±5%, 20/80%, CL = 5 pF, fIN = 156.25 MHz |
| Output-to-Output Skew | 25 ps typical, 50 ps max; condition: VDD = 3.3 V ±5% |
| Part-to-Part Skew | 250 ps max; condition: VDD = 3.3 V ±5% |
| Propagation Delay | 1.5 ns typical, 2 ns max; condition: VDD = 3.3 V ±5% |
| Additive Jitter | 8 fs RMS typical, 20 fs RMS max; condition: VDD = 3.3 V ±5%, fIN = 156.25 MHz, input slew rate = 2 V/ns, integration range = 12 kHz to 20 MHz |
| Output Impedance | 50 ohm typical; condition: VDD = 3.3 V ±5% |
| Output High Voltage | 0.8 x VDD min; condition: VDD = 2.5 V ±5%, IOH = 1 mA |
| Output Low Voltage | 0.2 x VDD max; condition: VDD = 2.5 V ±5%, IOL = 1 mA |
| Output Rise and Fall Time | 0.33 ns typical, 0.8 ns max; condition: VDD = 2.5 V ±5%, 20/80%, CL = 5 pF, fIN = 156.25 MHz |
| Output-to-Output Skew | 50 ps max; condition: VDD = 2.5 V ±5% |
| Part-to-Part Skew | 400 ps max; condition: VDD = 2.5 V ±5% |
| Propagation Delay | 1.5 ns typical, 2.5 ns max; condition: VDD = 2.5 V ±5% |
| Additive Jitter | 11 fs RMS typical, 27 fs RMS max; condition: VDD = 2.5 V ±5%, fIN = 156.25 MHz, input slew rate = 2 V/ns, integration range = 12 kHz to 20 MHz |
| Output Impedance | 52.5 ohm typical; condition: VDD = 2.5 V ±5% |
| Output High Voltage | 0.8 x VDD min; condition: VDD = 1.8 V ±5%, IOH = 1 mA |
| Output Low Voltage | 0.2 x VDD max; condition: VDD = 1.8 V ±5%, IOL = 1 mA |
| Output Rise and Fall Time | 0.38 ns typical, 1 ns max; condition: VDD = 1.8 V ±5%, 20/80%, CL = 5 pF, fIN = 156.25 MHz |
| Absolute Maximum Supply Voltage | 3.6 V max; condition: VDD |
| Absolute Maximum Clock Input Voltage | -0.5 V min, 3.6 V max; condition: CLKIN |
| Absolute Maximum Output Pin Voltage | -0.5 V min, VDD + 0.3 V max; condition: Yn output pins |
| Input Current | -20 mA min, 20 mA max; condition: absolute maximum rating |
| Continuous Output Current | -50 mA min, 50 mA max; condition: absolute maximum rating |
| Storage Temperature | -65°C to 150°C; condition: absolute maximum rating |
| HBM ESD Rating | ±9000 V; condition: ANSI/ESDA/JEDEC JS-001, all pins |
| CDM ESD Rating | ±1500 V; condition: JEDEC JESD22-C101, all pins |
| WSON Junction-to-Ambient Thermal Resistance | 163°C/W; condition: LMK1C1104 DQF WSON, 8 pins |
| TSSOP Junction-to-Ambient Thermal Resistance | 181.9°C/W; condition: LMK1C1104 PW TSSOP, 8 pins |
| WSON Junction-to-Case Top Thermal Resistance | 105.7°C/W; condition: LMK1C1104 DQF WSON, 8 pins |
| TSSOP Junction-to-Case Top Thermal Resistance | 76.6°C/W; condition: LMK1C1104 PW TSSOP, 8 pins |
| WSON Junction-to-Board Thermal Resistance | 84.2°C/W; condition: LMK1C1104 DQF WSON, 8 pins |
| TSSOP Junction-to-Board Thermal Resistance | 111.6°C/W; condition: LMK1C1104 PW TSSOP, 8 pins |
| Clock Input Pulldown Resistance | 300 kOhm typical; condition: CLKIN internal pulldown to GND |
| Output Enable Pulldown Resistance | 300 kOhm typical; condition: 1G internal pulldown to GND |
| Output Enable Function | HIGH enables outputs; LOW disables outputs; condition: 1G global output enable |
| Disabled Output State | Outputs switch low; condition: 1G is low |
| Input Tolerance | 3.3 V tolerant input; condition: at all supply voltages |
| Fail-Safe Input | Prevents output oscillation without input signal and allows input signals before VDD is supplied; condition: CLKIN fail-safe behavior |
| Datasheet Status | request_only |
Product Overview
The LMK1C1104 is a Texas Instruments LVCMOS clock buffer in the Signal_Chain category. It provides one LVCMOS clock input and four LVCMOS outputs, forming a 1:4 clock buffer fanout. The clock input uses LVCMOS thresholds, with 0.7 x VDD minimum input-high voltage and 0.3 x VDD maximum input-low voltage.
The device supports 1.8 V, 2.5 V, and 3.3 V operating supplies. Recommended ranges are 1.71 V to 1.89 V, 2.375 V to 2.625 V, and 3.135 V to 3.465 V. At 3.3 V, input and output frequency operation extends to 250 MHz; at 2.5 V or 1.8 V, operation extends to 200 MHz.
Package options include an 8-pin TSSOP measuring 3.00 mm x 4.40 mm and an 8-pin WSON measuring 2.00 mm x 2.00 mm. Thermal resistance values are specified for both packages. The global 1G output-enable pin enables outputs when high and disables outputs when low, with disabled outputs switching low.
Key Features
- 1:4 LVCMOS clock buffer fanout with four outputs
- Supports 1.8 V, 2.5 V, and 3.3 V supplies
- DC to 250 MHz input frequency at 3.3 V
- DC to 200 MHz input frequency at 2.5 V or 1.8 V
- 45% to 55% output duty cycle with 50% input
- 3 ms maximum start-up time before output active
- 5-cycle maximum output enable and disable timing
- 3.3 V tolerant input at all supply voltages
- Fail-safe input prevents output oscillation without input signal
- Disabled outputs switch low when 1G is low
Typical Applications
- LVCMOS clock distribution
- 1:4 clock fanout
- Multi-output timing trees
- Enable-controlled clock routing
- 3.3 V tolerant clock inputs
- Compact TSSOP clock layouts
- Compact WSON clock layouts
Procurement Notes
When requesting a quote for LMK1C1104, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the LMK1C1104?
The LMK1C1104 is a Texas Instruments LVCMOS clock buffer in the Signal_Chain category. It has one LVCMOS clock input and four LVCMOS outputs, providing a 1:4 fanout structure.
Which supply voltages does LMK1C1104 support?
The device supports 1.8 V, 2.5 V, and 3.3 V operation. Recommended operating ranges are 1.71 V to 1.89 V, 2.375 V to 2.625 V, and 3.135 V to 3.465 V.
What frequency range is specified for the LMK1C1104?
At VDD = 3.3 V, the input frequency range is DC to 250 MHz and output frequency is 250 MHz maximum. At 2.5 V or 1.8 V, both input and output operation are specified to 200 MHz.
What happens when the 1G output enable is low?
The 1G pin is the global output enable. A high level enables the outputs, while a low level disables them. When 1G is low, the disabled output state is specified as outputs switching low.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 12, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.