Specifications
| Type | Description |
|---|---|
| Part Number | LMK1C1106 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 14-pin TSSOP (PW), 5.00 mm x 4.40 mm nominal body |
| Clock Buffer Fanout | 1:6; LMK1C1106 device variant |
| Output Type | LVCMOS; clock outputs Y0-Y5 |
| Supply Voltage | 1.8 V, 2.5 V, or 3.3 V; nominal operating supply options |
| Recommended Supply Voltage Range | 3.135-3.465 V; 3.3-V supply |
| Recommended Supply Voltage Range | 2.375-2.625 V; 2.5-V supply |
| Recommended Supply Voltage Range | 1.71-1.89 V; 1.8-V supply |
| Operating Free-Air Temperature | -40 to 125 °C; recommended operating conditions |
| Operating Junction Temperature | -40 to 150 °C; recommended operating conditions |
| Storage Temperature | -65 to 150 °C; absolute maximum ratings |
| Maximum Input Frequency | 250 MHz; VDD = 3.3 V |
| Maximum Input Frequency | 200 MHz; VDD = 2.5 V or 1.8 V |
| Maximum Output Frequency | 250 MHz; VDD = 3.3 V |
| Maximum Output Frequency | 200 MHz; VDD = 2.5 V or 1.8 V |
| Output-to-Output Skew | 35 ps typ, 55 ps max; VDD = 3.3 V ±5%, rising edge Yn to Ym |
| Output-to-Output Skew | 55 ps max; VDD = 2.5 V ±5%, rising edge Yn to Ym |
| Output-to-Output Skew | 55 ps max; VDD = 1.8 V ±5%, rising edge Yn to Ym |
| Additive Jitter | 12 fs RMS typ, 20 fs RMS max; VDD = 3.3 V ±5%, fIN = 156.25 MHz, 1.6 V/ns slew, 12 kHz to 20 MHz |
| Additive Jitter | 15 fs RMS typ, 27 fs RMS max; VDD = 2.5 V ±5%, fIN = 156.25 MHz, 1.2 V/ns slew, 12 kHz to 20 MHz |
| Additive Jitter | 28 fs RMS typ, 60 fs RMS max; VDD = 1.8 V ±5%, fIN = 156.25 MHz, 1.2 V/ns slew, 12 kHz to 20 MHz |
| Propagation Delay | 1.3 ns typ, 2.2 ns max; VDD = 3.3 V ±5%, CLKIN rising edge to Yn |
| Propagation Delay | 1.5 ns typ, 2.5 ns max; VDD = 2.5 V ±5%, CLKIN rising edge to Yn |
| Propagation Delay | 1.5 ns typ, 3 ns max; VDD = 1.8 V ±5%, CLKIN rising edge to Yn |
| Output Duty Cycle | 45-55%; with 50% duty cycle input, all VDD levels |
| Output Rise and Fall Time | 0.3 ns typ, 0.7 ns max; VDD = 3.3 V ±5%, 20/80%, CL = 5 pF, fIN = 156.25 MHz |
| Output Rise and Fall Time | 0.33 ns typ, 0.8 ns max; VDD = 2.5 V ±5%, 20/80%, CL = 5 pF, fIN = 156.25 MHz |
| Output Rise and Fall Time | 0.38 ns typ, 1 ns max; VDD = 1.8 V ±5%, 20/80%, CL = 5 pF, fIN = 156.25 MHz |
| Input High Voltage | 0.7 x VDD min; CLKIN clock input |
| Input Low Voltage | 0.3 x VDD max; CLKIN clock input |
| Output Enable Time | 5 cycles max; from 1G rising edge crossing VIH to first Yn rising edge |
| Output Disable Time | 5 cycles max; from 1G falling edge crossing VIL to last Yn falling edge |
| ESD Rating HBM | ±9000 V; human body model per ANSI/ESDA/JEDEC JS-001, all pins |
| Datasheet Status | request_only |
Product Overview
The Texas Instruments LMK1C1106 is a 1:6 LVCMOS clock buffer for Signal_Chain timing distribution. The device accepts a CLKIN clock input and provides six LVCMOS clock outputs, Y0 through Y5. It supports nominal 1.8 V, 2.5 V, and 3.3 V supply operation, with recommended supply ranges of 1.71-1.89 V, 2.375-2.625 V, and 3.135-3.465 V respectively.
At 3.3 V, the LMK1C1106 supports 250 MHz maximum input and output frequency. At 2.5 V or 1.8 V, the maximum input and output frequency is 200 MHz. Timing specifications include output-to-output skew up to 55 ps maximum across supply options, propagation delay from 1.3 ns typical at 3.3 V, and output duty cycle of 45-55% with a 50% duty-cycle input.
The device is supplied in a 14-pin TSSOP (PW) package with a 5.00 mm x 4.40 mm nominal body. Operating free-air temperature is specified from -40 to 125 °C, and operating junction temperature is specified from -40 to 150 °C.
Key Features
- 1:6 fanout from one clock input
- LVCMOS outputs on Y0 through Y5
- Supports 1.8 V, 2.5 V, and 3.3 V supplies
- 250 MHz maximum frequency at 3.3 V
- 200 MHz maximum frequency at 2.5 V or 1.8 V
- 35 ps typical output-to-output skew at 3.3 V
- 12 fs RMS typical additive jitter at 3.3 V
- 45-55% output duty cycle with 50% input
- Five-cycle maximum output enable and disable timing
- ±9000 V HBM ESD rating on all pins
Typical Applications
- LVCMOS clock distribution
- One-to-six clock fanout
- Signal-chain timing distribution
- 156.25 MHz clock buffering
- Multi-output clock routing
- Low-skew clock tree design
- 1.8 V clock domains
- 2.5 V clock domains
- 3.3 V clock domains
Procurement Notes
When requesting a quote for LMK1C1106, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the LMK1C1106?
The LMK1C1106 is a Texas Instruments 1:6 LVCMOS clock buffer in the Signal_Chain category. It distributes one CLKIN clock input to six LVCMOS outputs identified as Y0 through Y5.
Which supply voltages does the LMK1C1106 support?
The LMK1C1106 supports nominal 1.8 V, 2.5 V, and 3.3 V operation. Recommended ranges are 1.71-1.89 V for 1.8 V, 2.375-2.625 V for 2.5 V, and 3.135-3.465 V for 3.3 V operation.
What maximum clock frequency is specified for this device?
At VDD = 3.3 V, the maximum input and output frequency is 250 MHz. At VDD = 2.5 V or 1.8 V, the maximum input and output frequency is 200 MHz.
What package is used for the LMK1C1106?
The LMK1C1106 is specified in a 14-pin TSSOP package, Texas Instruments package code PW, with a 5.00 mm x 4.40 mm nominal body size.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.