Specifications
| Type | Description |
|---|---|
| Part Number | LMK3H0102 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | RER TQFN-16, 3.0 mm x 3.0 mm |
| Output Configuration | 2 differential outputs or up to 5 single-ended LVCMOS outputs; Device output capability |
| Reference Requirement | No external crystal or external clock reference required; Integrated BAW resonator |
| PCIe Compliance | PCIe Gen 1 to Gen 7 compliant; Common Clock with or without SSC, SRNS, and SRIS |
| Output Frequency Range | 2.5 MHz to 400 MHz; LP-HCSL clock output characteristics |
| LVCMOS Output Frequency | Up to 200 MHz; 1.8 V, 2.5 V, or 3.3 V LVCMOS outputs |
| Total Frequency Stability | -25 ppm to +25 ppm; Includes temperature variation, 10-year aging at 25°C, solder shift, hysteresis, and initial frequency accuracy |
| Supply Voltage | 1.71 V min, 1.8 V nominal, 1.89 V max; VDD recommended operating condition, 1.8 V rail |
| Supply Voltage | 2.375 V min, 2.5 V nominal, 2.625 V max; VDD recommended operating condition, 2.5 V rail |
| Supply Voltage | 3.135 V min, 3.3 V nominal, 3.465 V max; VDD recommended operating condition, 3.3 V rail |
| Output Supply Voltage | 1.71 V min, 1.8 V nominal, 1.89 V max; VDDO recommended operating condition, 1.8 V rail |
| Output Supply Voltage | 2.375 V min, 2.5 V nominal, 2.625 V max; VDDO recommended operating condition, 2.5 V rail |
| Output Supply Voltage | 3.135 V min, 3.3 V nominal, 3.465 V max; VDDO recommended operating condition, 3.3 V rail |
| Ambient Temperature | -40°C to +85°C; Recommended operating condition |
| Junction Temperature | -40°C to +105°C; Recommended operating condition |
| Power Supply Ramp Time | 0.05 ms to 5 ms; VDD = 1.8 V |
| Power Supply Ramp Time | 0.05 ms to 5 ms; VDD = 2.5 V or 3.3 V |
| Device Supply Absolute Maximum | -0.3 V to 3.9 V; VDD absolute maximum rating |
| Output Supply Absolute Maximum | -0.3 V to 3.9 V; VDDO absolute maximum rating |
| Logic Input Voltage Absolute Maximum | -0.3 V to 3.9 V; VIN, VDD = VDDO = -0.3 V to -3.9 V |
| Maximum Junction Temperature | 105°C; Absolute maximum rating |
| ESD Rating HBM | ±2000 V; ANSI/ESDA/JEDEC JS-001, all pins |
| ESD Rating CDM | ±500 V; JEDEC JS-002, all pins |
| LP-HCSL Output Low Voltage | -60 mV min, 25 mV max; Undershoot included |
| LP-HCSL Overshoot Voltage | 150 mV max; Vmax - VOH |
| LP-HCSL Static Differential Impedance | 80.75 Ω min, 85 Ω typ, 91.25 Ω max; 85 Ω setting |
| LP-HCSL Static Differential Impedance | 95 Ω min, 100 Ω typ, 105 Ω max; 100 Ω setting |
| Output Slew Rate | 2.1 V/ns min, 3.1 V/ns max; Measured -150 mV to +150 mV, OUTx_SLEW_RATE = 0 |
| Output Slew Rate | 2.0 V/ns min, 3.2 V/ns max; Measured -150 mV to +150 mV, OUTx_SLEW_RATE = 1 |
| Output Slew Rate | 1.7 V/ns min, 2.8 V/ns max; Measured -150 mV to +150 mV, OUTx_SLEW_RATE = 2 |
| Output Slew Rate | 1.4 V/ns min, 2.7 V/ns max; Measured -150 mV to +150 mV, OUTx_SLEW_RATE = 3 |
| Output Duty Cycle | 47% min, 53% max; LP-HCSL output duty cycle, visible table excerpt |
| Startup Time | <1.5 ms; Device startup |
| Output-to-Output Skew | <50 ps; Between clock outputs |
| PCIe Gen 3 Common Clock Jitter | 135.3 fs max; With SSC, PCIe limit 1 ps |
| PCIe Gen 4 Common Clock Jitter | 135.3 fs max; With SSC, PCIe limit 500 fs |
| PCIe Gen 5 Common Clock Jitter | 57.5 fs max; With SSC, PCIe limit 150 fs |
| PCIe Gen 6 Common Clock Jitter | 34.5 fs max; With SSC, PCIe limit 100 fs |
| PCIe Gen 7 Common Clock Jitter | 29.6 fs max; With SSC, PCIe limit 67 fs |
| Preprogrammed SSC Modulation Depth | -0.1%, -0.25%, -0.3%, -0.5% down spread; At 200 MHz FOD frequency |
| Register Programmable SSC Modulation Depth | -0.1% to -3% down spread or ±0.05% to ±1.5% center spread; Register programmable SSC |
| Power Supply Noise Rejection | -93.1 dBc; 500 kHz switching noise, LP-HCSL outputs |
| Datasheet Status | request_only |
Product Overview
The LMK3H0102 is a Texas Instruments reference-less PCIe clock generator for Signal_Chain designs. Its integrated BAW resonator removes the need for an external crystal or external clock reference, reducing the required timing components around the clock source. The output structure supports either 2 differential outputs or up to 5 single-ended LVCMOS outputs.
For PCIe timing, the device is specified as PCIe Gen 1 to Gen 7 compliant for Common Clock operation with or without SSC, as well as SRNS and SRIS conditions. LP-HCSL outputs cover 2.5 MHz to 400 MHz, while 1.8 V, 2.5 V, or 3.3 V LVCMOS outputs support operation up to 200 MHz. Total frequency stability is specified from -25 ppm to +25 ppm.
The device is supplied in an RER TQFN-16 package measuring 3.0 mm x 3.0 mm. Recommended operating conditions include 1.8 V, 2.5 V, and 3.3 V VDD and VDDO rails, -40°C to +85°C ambient operation, and -40°C to +105°C junction operation.
Key Features
- Reference-less PCIe clock generator with integrated BAW resonator
- No external crystal or clock reference required
- PCIe Gen 1 to Gen 7 compliant timing
- 2 differential outputs or up to 5 LVCMOS outputs
- LP-HCSL output frequency range from 2.5 MHz to 400 MHz
- LVCMOS output frequency up to 200 MHz
- Total frequency stability from -25 ppm to +25 ppm
- Startup time below 1.5 ms
- Output-to-output skew below 50 ps
- Register programmable SSC depth options
Typical Applications
- PCIe common clock timing
- PCIe SRNS clocking
- PCIe SRIS clocking
- LP-HCSL clock distribution
- LVCMOS clock generation
- Reference-less board timing
- Multi-output signal-chain timing
Procurement Notes
When requesting a quote for LMK3H0102, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
Does LMK3H0102 require an external crystal reference?
No. The extracted datasheet facts state that LMK3H0102 uses an integrated BAW resonator and requires no external crystal or external clock reference.
What output formats does LMK3H0102 support?
The device supports 2 differential outputs or up to 5 single-ended LVCMOS outputs. LP-HCSL clock outputs are specified from 2.5 MHz to 400 MHz, and LVCMOS outputs support operation up to 200 MHz.
Which PCIe generations are covered by LMK3H0102?
LMK3H0102 is specified as PCIe Gen 1 to Gen 7 compliant under Common Clock operation with or without SSC, and also under SRNS and SRIS conditions.
What supply rails are specified for LMK3H0102?
Recommended VDD and VDDO operating rails include 1.8 V, 2.5 V, and 3.3 V options, with listed min and max ranges for each rail in the extracted datasheet facts.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.