Specifications
| Type | Description |
|---|---|
| Part Number | LMK5B12204 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | RGZ VQFN-48, 7 mm x 7 mm |
| DPLL Count | 1; integrated high-performance digital phase-locked loop |
| APLL Count | 2; integrated analog phase-locked loops |
| DPLL Loop Bandwidth | 1 mHz to 4 kHz; programmable DPLL loop bandwidth |
| DCO Adjustment Resolution | < 1 ppt per step; for IEEE 1588 PTP clock steering |
| DPLL Reference Inputs | 2; differential or single-ended inputs |
| Input Frequency Range | 1 Hz to 800 MHz; DPLL input frequency range, includes 1PPS |
| Clock Outputs | 4 differential outputs; programmable output drivers |
| Output Frequency | Up to 1250 MHz; clock output frequency |
| Output Formats | AC-LVPECL, AC-CML, AC-LVDS, HCSL, 1.8 V LVCMOS; programmable output formats |
| RMS Jitter | 32 fs typical; 312.5 MHz output, 4 MHz 1st-order high-pass filter |
| RMS Jitter | 44 fs typical; 156.25 MHz output, 4 MHz 1st-order high-pass filter |
| RMS Jitter | 50 fs typical, 80 fs maximum; 312.5 MHz output |
| RMS Jitter | 60 fs typical, 90 fs maximum; 156.25 MHz output |
| APLL1 VCO Type | BAW VCO; TI Bulk Acoustic Wave technology |
| APLL2 VCO Type | LC VCO; second frequency and/or synchronization domain |
| VCO Frequency | 2500 MHz; LMK5B12204 device comparison table |
| Core Supply Voltage | 3.3 V |
| Output Supply Voltage | 1.8 V, 2.5 V, or 3.3 V; OUT0 to OUT3 |
| Operating Temperature Range | -40°C to +85°C |
| Serial Interfaces | I2C, 3-wire SPI, or 4-wire SPI; programming and control |
| PCIe Compliance | PCIe Gen 1 to Gen 6 compliant; clock outputs |
| EEPROM | Integrated EEPROM; custom system configurations on startup |
| Input Pins | PRIREF_P/N and SECREF_P/N; primary and secondary reference clock inputs |
| XO Input | XO_P/N; differential or single-ended XO/TCXO/OCXO input reference to APLLs |
| LVCMOS XO Input Level | Up to 2.5 V; single-ended LVCMOS on XO_P with XO_N pulled down |
| Datasheet Status | request_only |
Product Overview
The LMK5B12204 is a Texas Instruments Signal_Chain network synchronizer jitter cleaner built around one integrated high-performance DPLL and two integrated APLLs. Its programmable DPLL loop bandwidth spans 1 mHz to 4 kHz, and the DCO adjustment resolution is less than 1 ppt per step for IEEE 1588 PTP clock steering.
The device accepts two DPLL reference inputs on PRIREF_P/N and SECREF_P/N, configurable as differential or single-ended inputs. The DPLL input frequency range is 1 Hz to 800 MHz, including 1PPS. A separate XO_P/N input supports differential or single-ended XO, TCXO, or OCXO references to the APLLs; single-ended LVCMOS on XO_P is supported up to 2.5 V with XO_N pulled down.
Output capability includes four programmable differential clock outputs up to 1250 MHz. Supported output formats are AC-LVPECL, AC-CML, AC-LVDS, HCSL, and 1.8 V LVCMOS, with PCIe Gen 1 to Gen 6 compliance. The device uses a 3.3 V core supply, 1.8 V, 2.5 V, or 3.3 V output supplies, integrated EEPROM for startup configurations, and I2C, 3-wire SPI, or 4-wire SPI control in an RGZ VQFN-48 package.
Key Features
- One integrated high-performance DPLL
- Two integrated analog phase-locked loops
- Programmable DPLL bandwidth from 1 mHz to 4 kHz
- Less than 1 ppt DCO adjustment resolution
- Two differential or single-ended DPLL reference inputs
- 1 Hz to 800 MHz input range including 1PPS
- Four programmable differential outputs up to 1250 MHz
- AC-LVPECL, AC-CML, AC-LVDS, HCSL, and LVCMOS formats
- 32 fs typical RMS jitter at 312.5 MHz filtered
- Integrated EEPROM for startup configuration storage
Typical Applications
- Network synchronization
- IEEE 1588 PTP clock steering
- PCIe Gen 1 to Gen 6 clocking
- 1PPS referenced timing
- Dual synchronization domains
- XO, TCXO, or OCXO referenced systems
Procurement Notes
When requesting a quote for LMK5B12204, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the LMK5B12204?
The LMK5B12204 is a Texas Instruments network synchronizer jitter cleaner in the Signal_Chain category. It integrates one high-performance DPLL and two APLLs for clock synchronization and jitter-cleaning functions.
What reference inputs does the LMK5B12204 support?
The device has two DPLL reference inputs on PRIREF_P/N and SECREF_P/N. These inputs can be differential or single-ended, with a DPLL input frequency range from 1 Hz to 800 MHz, including 1PPS.
Which output formats are available on the LMK5B12204?
The four programmable differential outputs support AC-LVPECL, AC-CML, AC-LVDS, HCSL, and 1.8 V LVCMOS formats. Clock output frequency is specified up to 1250 MHz.
What package is used for the LMK5B12204?
The LMK5B12204 is specified in an RGZ VQFN-48 package measuring 7 mm x 7 mm. The operating temperature range is -40°C to +85°C.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 7, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.