Specifications
| Type | Description |
|---|---|
| Part Number | LMK61E2 |
| Manufacturer | Texas Instruments |
| Product Type | Serial EEPROM |
| Category | Memory & Storage |
| Package / Case | SIA QFM, 8-pin, 7.00 mm x 5.00 mm |
| Component Type | Other |
| Default Output Frequency | 156.25 MHz; condition: LMK61E2 default factory-programmed setting |
| Default Output Format | LVPECL; condition: LMK61E2 default factory-programmed setting |
| Alternate Orderable Default Output | 156.25 MHz LVDS; condition: Part number LMK61E2BAA |
| Alternate Orderable Default Output | 125 MHz LVDS; condition: Part number LMK61E2BBA |
| Typical Jitter | 90 fs RMS; condition: fOUT > 100 MHz |
| PSRR | -70 dBc; condition: supply noise immunity feature |
| LVPECL Output Frequency Range | 10 to 1000 MHz; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| LVDS Output Frequency Range | 10 to 900 MHz; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| HCSL Output Frequency Range | 10 to 400 MHz; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| Device Supply Voltage | 3.135 V min, 3.3 V nom, 3.465 V max; condition: recommended operating conditions |
| Ambient Temperature Range | -40°C min, 25°C nom, 85°C max; condition: recommended operating conditions |
| Junction Temperature | 125°C max; condition: recommended operating conditions |
| VDD Power-Up Ramp Time | 0.1 ms min, 100 ms max; condition: recommended operating conditions |
| Absolute Maximum Device Supply Voltage | -0.3 V to 3.6 V; condition: operating free-air temperature range |
| Absolute Maximum Logic Input Voltage | -0.3 V to VDD + 0.3 V; condition: operating free-air temperature range |
| Absolute Maximum Clock Output Voltage | -0.3 V to VDD + 0.3 V; condition: operating free-air temperature range |
| Absolute Maximum Junction Temperature | 150°C; condition: absolute maximum ratings |
| Storage Temperature Range | -40°C to 125°C; condition: absolute maximum ratings |
| ESD Rating HBM | ±2000 V; condition: Human-body model per ANSI/ESDA/JEDEC JS-001 |
| ESD Rating CDM | ±500 V; condition: Charged-device model per JEDEC JESD22-C101 |
| LVPECL Supply Current | 162 mA typ, 208 mA max; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| LVDS Supply Current | 152 mA typ, 196 mA max; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| HCSL Supply Current | 155 mA typ, 196 mA max; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| Power-Down Current | 136 mA typ; condition: OE = GND, output disabled |
| LVPECL Output Voltage Swing | 700 mV min, 800 mV typ, 1200 mV max; condition: VOD = VOH - VOL, VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| LVPECL Output Common-Mode Voltage | VDD - 1.55 V; condition: VOS, VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| LVPECL Rise/Fall Time | 120 ps typ, 200 ps max; condition: 20% to 80%, verified by characterization |
| LVPECL Phase Noise Floor | -165 dBc/Hz typ; condition: 156.25 MHz, offset frequency > 10 MHz |
| LVPECL Output Duty Cycle | 45% min, 55% max; condition: verified by characterization |
| LVDS Output Voltage Swing | 300 mV min, 390 mV typ, 480 mV max; condition: VOD = VOH - VOL, VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| LVDS Output Common-Mode Voltage | 1.2 V typ; condition: VOS, VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| LVDS Rise/Fall Time | 150 ps typ, 250 ps max; condition: 20% to 80%, verified by characterization |
| LVDS Phase Noise Floor | -162 dBc/Hz typ; condition: 156.25 MHz, offset frequency > 10 MHz |
| LVDS Output Duty Cycle | 45% min, 55% max; condition: verified by characterization |
| LVDS Differential Output Impedance | 125 ohm typ; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| HCSL Output High Voltage | 600 mV min, 850 mV max; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| HCSL Output Low Voltage | -100 mV min, 100 mV max; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| HCSL Absolute Crossing Voltage | 250 mV min, 475 mV max; condition: measured from -150 mV to +150 mV on differential waveform, verified by design |
| HCSL Crossing Voltage Variation | 0 mV min, 140 mV max; condition: VCROSS-DELTA, verified by design |
| HCSL Slew Rate | 0.8 V/ns min, 2 V/ns max; condition: verified by characterization |
| HCSL Phase Noise Floor | -164 dBc/Hz typ; condition: 100 MHz, offset frequency > 10 MHz |
| HCSL Output Duty Cycle | 45% min, 55% max; condition: verified by characterization |
| OE Input High Voltage | 1.4 V min; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| OE Input Low Voltage | 0.6 V max; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| OE Input High Current | -40 uA min, 40 uA max; condition: VIH = VDD |
| OE Input Low Current | -40 uA min, 40 uA max; condition: VIL = GND |
| OE Input Capacitance | 2 pF typ; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| ADD Input High Voltage | 1.4 V min; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| ADD Input Low Voltage | 0.4 V max; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| ADD Input High Current | -40 uA min, 40 uA max; condition: VIH = VDD |
| ADD Input Low Current | -40 uA min, 40 uA max; condition: VIL = GND |
| ADD Input Capacitance | 2 pF typ; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| Total Frequency Tolerance | -50 ppm min, 50 ppm max; condition: all output formats, frequency bands, junction temperature up to 125°C; includes initial tolerance, temperature and supply variation, solder reflow, and 10-year aging |
| Power-On Reset Threshold Voltage | 2.72 V min, 2.95 V max; condition: VDD = 3.3 V ±5%, TA = -40°C to 85°C |
| Allowable Voltage Droop | 0.1 V max; condition: VDD power-on/reset characteristics |
| Junction-to-Ambient Thermal Resistance | 54°C/W at 0 LFM, 44°C/W at 200 LFM, 41.2°C/W at 400 LFM; condition: SIA QFM 8-pin package, 4-layer JEDEC board |
| Junction-to-Case Top Thermal Resistance | 34°C/W; condition: SIA QFM 8-pin package, 0 LFM airflow |
| Junction-to-Board Thermal Resistance | 36.7°C/W; condition: SIA QFM 8-pin package, 0 LFM airflow |
| Junction-to-Top Characterization Parameter | 11.2°C/W at 0 LFM, 16.9°C/W at 200 LFM, 21.9°C/W at 400 LFM; condition: SIA QFM package |
| Junction-to-Board Characterization Parameter | 36.7°C/W at 0 LFM, 37.8°C/W at 200 LFM, 38.9°C/W at 400 LFM; condition: SIA QFM package |
| Control Interface | I2C; condition: device registers and EEPROM settings programmable in-system |
| SCL Pin Function | I2C serial clock, open-drain; condition: requires external pullup resistor to VDD |
| SDA Pin Function | I2C serial data, bidirectional open-drain; condition: requires external pullup resistor to VDD |
| OE Pin Function | Output enable with internal pullup; condition: low disables output pair and sets outputs high impedance |
| ADD Pin Address Selection | Open = I2C address LSB 01, VDD = LSB 10, GND = LSB 00; condition: ADD pin configuration |
| Datasheet Status | request_only |
Product Overview
The LMK61E2 is a Texas Instruments programmable oscillator with EEPROM for Signal_Chain clock generation. Its default factory-programmed configuration is 156.25 MHz LVPECL, while LMK61E2BAA provides a 156.25 MHz LVDS orderable default and LMK61E2BBA provides a 125 MHz LVDS orderable default. Device registers and EEPROM settings are programmable in-system through I2C.
Output-format coverage includes LVPECL from 10 to 1000 MHz, LVDS from 10 to 900 MHz, and HCSL from 10 to 400 MHz under 3.3 V ±5% supply and -40°C to 85°C ambient conditions. The device specifies 90 fs RMS typical jitter for output frequencies above 100 MHz and -70 dBc PSRR for supply-noise immunity.
The package is SIA QFM, 8-pin, 7.00 mm x 5.00 mm. Recommended operating conditions include 3.135 V to 3.465 V supply, up to 125°C junction temperature, and 0.1 ms to 100 ms VDD ramp time. SCL and SDA are open-drain I2C pins requiring external pullup resistors to VDD, while OE disables the differential output pair when driven low.
Key Features
- 156.25 MHz LVPECL factory-programmed default output
- Orderable LVDS defaults at 156.25 MHz and 125 MHz
- 90 fs RMS typical jitter above 100 MHz
- -70 dBc PSRR supply-noise immunity feature
- LVPECL output range from 10 to 1000 MHz
- LVDS output range from 10 to 900 MHz
- HCSL output range from 10 to 400 MHz
- I2C-programmable registers and EEPROM settings
- OE pin disables outputs to high impedance
- SIA QFM 8-pin 7.00 mm x 5.00 mm package
Typical Applications
- LVPECL clock generation
- LVDS clock generation
- HCSL clock generation
- 156.25 MHz clock sources
- 125 MHz LVDS clock sources
- I2C-programmable oscillator designs
- Differential clock output modules
Procurement Notes
When requesting a quote for LMK61E2, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For memory and storage sourcing, density, organization, speed grade, voltage, package, temperature grade, date code, lifecycle status and original packing condition should be verified before approval.
FAQ
What is the LMK61E2 default factory-programmed output?
The LMK61E2 default factory-programmed output is 156.25 MHz with an LVPECL output format. Alternate orderable defaults include 156.25 MHz LVDS for LMK61E2BAA and 125 MHz LVDS for LMK61E2BBA.
What output frequency ranges does LMK61E2 support?
Under 3.3 V ±5% supply and -40°C to 85°C ambient conditions, LMK61E2 supports LVPECL from 10 to 1000 MHz, LVDS from 10 to 900 MHz, and HCSL from 10 to 400 MHz.
How are LMK61E2 settings programmed in-system?
LMK61E2 uses an I2C control interface for device registers and EEPROM settings. SCL is an open-drain serial clock, and SDA is bidirectional open-drain serial data; both require external pullup resistors to VDD.
What are the recommended LMK61E2 operating supply limits?
The recommended device supply voltage is 3.135 V minimum, 3.3 V nominal, and 3.465 V maximum. The specified ambient temperature range is -40°C to 85°C, with junction temperature up to 125°C.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 28, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.