Specifications
| Type | Description |
|---|---|
| Part Number | PCM1808 |
| Manufacturer | Texas Instruments |
| Product Type | ADC |
| Category | Signal Chain |
| Package / Case | 14-pin TSSOP (PW), body size 4.40 mm x 5.00 mm |
| ADC Resolution | 24 bits; condition: Stereo delta-sigma A/D converter |
| Analog Input Type | Single-ended voltage input; condition: VINL and VINR analog inputs |
| Full-Scale Analog Input Voltage | 3 Vp-p; condition: VCC = 5 V, -0 dB |
| Sampling Frequency | 8 kHz min, 48 kHz typ, 96 kHz max; condition: Audio ADC operation |
| Oversampling Frequency | 64x; condition: Delta-sigma modulator with decimation filter |
| Audio Data Interface Formats | 24-bit I2S, 24-bit left-justified; condition: PCM audio interface |
| Audio Data Format | MSB-first, 2s complement; condition: 24-bit audio data |
| Analog Supply Voltage | 4.5 V min, 5 V nom, 5.5 V max; condition: Recommended operating conditions |
| Digital Supply Voltage | 2.7 V min, 3.3 V nom, 3.6 V max; condition: Recommended operating conditions |
| System Clock Frequency | 2.048 MHz min, 49.152 MHz max; condition: Recommended operating conditions |
| System Clock Frequency at 256fs | 2.048 MHz min, 12.288 MHz typ, 24.576 MHz max; condition: fs = 8 kHz to 96 kHz |
| System Clock Frequency at 384fs | 3.072 MHz min, 18.432 MHz typ, 36.864 MHz max; condition: fs = 8 kHz to 96 kHz |
| System Clock Frequency at 512fs | 4.096 MHz min, 24.576 MHz typ, 49.152 MHz max; condition: fs = 8 kHz to 96 kHz |
| THD+N | -93 dB typ, -87 dB max; condition: VIN = -0.5 dB, fs = 48 kHz |
| THD+N | -87 dB typ; condition: VIN = -0.5 dB, fs = 96 kHz, system clock = 256fs |
| Dynamic Range | 95 dB min, 99 dB typ; condition: fs = 48 kHz, A-weighted |
| Dynamic Range | 101 dB typ; condition: fs = 96 kHz, A-weighted, system clock = 256fs |
| Signal-to-Noise Ratio | 95 dB min, 99 dB typ; condition: fs = 48 kHz, A-weighted |
| Signal-to-Noise Ratio | 101 dB typ; condition: fs = 96 kHz, A-weighted, system clock = 256fs |
| Channel Separation | 93 dB min, 97 dB typ; condition: fs = 48 kHz |
| Channel Separation | 91 dB typ; condition: fs = 96 kHz, system clock = 256fs |
| Analog Input Voltage | 0.6 x VCC Vp-p; condition: Analog input full-scale relation |
| Analog Input Center Voltage | 0.5 x VCC V; condition: VREF center voltage |
| Analog Input Impedance | 60 kOhm; condition: VINL and VINR analog inputs |
| Antialiasing Filter Frequency Response | -3 dB at 1.3 MHz; condition: Integrated analog antialiasing filter |
| Digital Filter Passband | 0.454 x fs Hz; condition: Oversampling decimation filter |
| Digital Filter Stopband | 0.583 x fs Hz; condition: Oversampling decimation filter |
| Digital Filter Pass-Band Ripple | +/-0.05 dB; condition: Oversampling decimation filter |
| Digital Filter Stop-Band Attenuation | -65 dB; condition: Oversampling decimation filter |
| Digital Filter Delay Time | 17.4/fs; condition: Digital decimation filter |
| High-Pass Filter Frequency Response | -3 dB at 0.019 x fs / 1000; condition: On-chip HPF |
| Analog Supply Current | 8.6 mA typ, 11 mA max; condition: fs = 48 kHz or 96 kHz, minimum load on LRCK, BCK, DOUT |
| Digital Supply Current | 5.9 mA typ, 8 mA max; condition: fs = 48 kHz, minimum load on LRCK, BCK, DOUT |
| Digital Supply Current | 10.2 mA typ; condition: fs = 96 kHz, system clock = 256fs |
| Power Dissipation | 62 mW typ, 81 mW max; condition: fs = 48 kHz |
| Power Dissipation | 77 mW typ; condition: fs = 96 kHz, system clock = 256fs |
| Powered-Down Analog Supply Current | 1 uA typ; condition: Power-down and reset enabled by halting SCKI, BCK, LRCK |
| Powered-Down Digital Supply Current | 150 uA typ; condition: Power-down and reset enabled by halting SCKI, BCK, LRCK |
| Powered-Down Power Dissipation | 500 uW typ; condition: Power-down and reset enabled by halting SCKI, BCK, LRCK |
| Operating Ambient Temperature | -40°C min, 85°C max; condition: Recommended operating conditions |
| Junction Temperature | 150°C max; condition: Recommended operating conditions and absolute maximum ratings |
| Datasheet Status | request_only |
Product Overview
The PCM1808 is a Texas Instruments stereo audio ADC for Signal_Chain designs requiring 24-bit delta-sigma conversion. Its analog inputs are single-ended voltage inputs on VINL and VINR, with 60 kOhm input impedance and a full-scale relation of 0.6 x VCC Vp-p. At VCC = 5 V and -0 dB input level, the full-scale analog input voltage is 3 Vp-p, centered around 0.5 x VCC V through the VREF center voltage.
The converter uses a 64x oversampling delta-sigma modulator with a decimation filter. Audio output data is MSB-first, 2s complement, and can be formatted as 24-bit I2S or 24-bit left-justified PCM data. Sampling frequency spans 8 kHz to 96 kHz, with supported system clock operation from 2.048 MHz to 49.152 MHz and 256fs, 384fs, or 512fs clocking ranges.
For implementation, the device is housed in a 14-pin TSSOP (PW) package with a 4.40 mm x 5.00 mm body. Recommended operating supplies are 4.5 V to 5.5 V analog and 2.7 V to 3.6 V digital, across -40°C to 85°C ambient operation. Performance data includes 99 dB typ dynamic range and SNR at 48 kHz, with 101 dB typ values at 96 kHz and 256fs clocking.
Key Features
- 24-bit stereo delta-sigma A/D conversion
- Single-ended VINL and VINR voltage inputs
- 8 kHz to 96 kHz sampling frequency range
- 64x oversampling with digital decimation filter
- 24-bit I2S and left-justified audio interfaces
- MSB-first, 2s complement audio data format
- 99 dB typ A-weighted dynamic range at 48 kHz
- 101 dB typ A-weighted SNR at 96 kHz
- Integrated analog antialiasing filter, -3 dB at 1.3 MHz
- Power-down enabled by halting SCKI, BCK, and LRCK
Typical Applications
- Stereo audio capture
- PCM audio input stages
- I2S audio interface designs
- Left-justified audio data systems
- Single-ended analog audio inputs
- 48 kHz audio conversion
- 96 kHz audio conversion
- Low-power audio standby designs
Procurement Notes
When requesting a quote for PCM1808, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of converter is the PCM1808?
The PCM1808 is a Texas Instruments stereo audio ADC. The extracted specifications identify it as a 24-bit stereo delta-sigma A/D converter with single-ended voltage inputs on VINL and VINR.
Which audio interface formats does PCM1808 support?
The PCM1808 supports 24-bit I2S and 24-bit left-justified PCM audio interface formats. Its audio output data format is MSB-first, 2s complement for 24-bit audio data.
What sampling frequencies are specified for PCM1808 operation?
The specified audio ADC sampling frequency range is 8 kHz minimum, 48 kHz typical, and 96 kHz maximum. System clock ranges are also provided for 256fs, 384fs, and 512fs operation across 8 kHz to 96 kHz.
What supply voltages are recommended for PCM1808?
Recommended operating conditions specify a 4.5 V to 5.5 V analog supply, with 5 V nominal, and a 2.7 V to 3.6 V digital supply, with 3.3 V nominal.
What package is used for the PCM1808?
The PCM1808 is specified in a 14-pin TSSOP package with the PW package designation. The listed body size is 4.40 mm x 5.00 mm.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 28, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.