Specifications
| Type | Description |
|---|---|
| Part Number | SIZF4800LDT |
| Manufacturer | Vishay |
| Product Type | LDO Regulator |
| Category | Power Management |
| Package / Case | PowerPAIR 3 x 3FS, 3.3 mm x 3.3 mm |
| Drain-Source Voltage | 80 V; absolute maximum rating, TA=25°C unless otherwise noted |
| Gate-Source Voltage | ±20 V; absolute maximum rating, TA=25°C unless otherwise noted |
| Continuous Drain Current | 36 A; TC=25°C, TJ=150°C |
| Continuous Drain Current | 29 A; TC=70°C, TJ=150°C |
| Continuous Drain Current | 10 A; TA=25°C, surface mounted on 1 in x 1 in FR4 board, t=10 s, TJ=150°C |
| Continuous Drain Current | 8 A; TA=70°C, surface mounted on 1 in x 1 in FR4 board, t=10 s, TJ=150°C |
| Pulsed Drain Current | 40 A; t=100 µs |
| Continuous Source Current | 52 A; MOSFET diode conduction, TC=25°C |
| Continuous Source Current | 4.1 A; MOSFET diode conduction, TA=25°C, surface mounted on 1 in x 1 in FR4 board, t=10 s |
| Single Pulse Avalanche Current | 16 A; L=0.1 mH |
| Single Pulse Avalanche Energy | 13 mJ; L=0.1 mH |
| Maximum Power Dissipation | 56.8 W; TC=25°C |
| Maximum Power Dissipation | 36.4 W; TC=70°C |
| Maximum Power Dissipation | 4.5 W; TA=25°C, surface mounted on 1 in x 1 in FR4 board, t=10 s |
| Maximum Power Dissipation | 2.9 W; TA=70°C, surface mounted on 1 in x 1 in FR4 board, t=10 s |
| Operating Junction and Storage Temperature Range | -55 to +150 °C; TJ, Tstg |
| Soldering Peak Temperature | 260 °C; soldering recommendations |
| Junction-to-Ambient Thermal Resistance | 22 °C/W typ, 28 °C/W max; t≤10 s, surface mounted on 1 in x 1 in FR4 board |
| Junction-to-Ambient Thermal Resistance | 64 °C/W max; steady state, surface mounted on 1 in x 1 in FR4 board |
| Junction-to-Case Thermal Resistance | 1.7 °C/W typ, 2.2 °C/W max; drain, steady state |
| Drain-Source Breakdown Voltage | 80 V min; VGS=0 V, ID=250 µA |
| Gate-Source Threshold Voltage | 1 V min, 2 V max; VDS=VGS, ID=250 µA |
| Gate-Source Leakage | ±100 nA max; VDS=0 V, VGS=±20 V |
| Zero Gate Voltage Drain Current | 1 µA max; VDS=80 V, VGS=0 V |
| Zero Gate Voltage Drain Current | 5 µA max; VDS=80 V, VGS=0 V, TJ=55°C |
| Drain-Source On-State Resistance | 0.0160 Ω typ, 0.019 Ω max; VGS=10 V, ID=10 A, pulse test |
| Drain-Source On-State Resistance | 0.0185 Ω typ, 0.0238 Ω max; VGS=4.5 V, ID=5 A, pulse test |
| Forward Transconductance | 50 S typ; VDS=10 V, ID=25 A, pulse test |
| Input Capacitance | 950 pF typ; VDS=40 V, VGS=0 V, f=1 MHz |
| Output Capacitance | 110 pF typ; VDS=40 V, VGS=0 V, f=1 MHz |
| Reverse Transfer Capacitance | 10 pF typ; VDS=40 V, VGS=0 V, f=1 MHz |
| Reverse Transfer to Input Capacitance Ratio | 0.010 typ, 0.020 max; Crss/Ciss |
| Total Gate Charge | 15 nC typ, 23 nC max; VDS=40 V, VGS=10 V, ID=10 A |
| Total Gate Charge | 7.1 nC typ, 11 nC max; VDS=40 V, VGS=4.5 V, ID=10 A |
| Gate-Source Charge | 3.1 nC typ; VDS=40 V, VGS=4.5 V, ID=10 A |
| Gate-Drain Charge | 2 nC typ; VDS=40 V, VGS=4.5 V, ID=10 A |
| Gate Resistance | 0.20 Ω min, 0.95 Ω typ, 1.9 Ω max; f=1 MHz |
| Turn-On Delay Time | 10 ns typ, 20 ns max; VDD=40 V, RL=4 Ω, ID≈10 A, VGEN=10 V, Rg=1 Ω |
| Rise Time | 5 ns typ, 10 ns max; VDD=40 V, RL=4 Ω, ID≈10 A, VGEN=10 V, Rg=1 Ω |
| Turn-Off Delay Time | 17 ns typ, 35 ns max; VDD=40 V, RL=4 Ω, ID≈10 A, VGEN=10 V, Rg=1 Ω |
| Fall Time | 5 ns typ, 10 ns max; VDD=40 V, RL=4 Ω, ID≈10 A, VGEN=10 V, Rg=1 Ω |
| Turn-On Delay Time | 13 ns typ, 25 ns max; VDD=40 V, RL=4 Ω, ID≈10 A, VGEN=4.5 V, Rg=1 Ω |
| Rise Time | 17 ns typ, 35 ns max; VDD=40 V, RL=4 Ω, ID≈10 A, VGEN=4.5 V, Rg=1 Ω |
| Turn-Off Delay Time | 16 ns typ, 30 ns max; VDD=40 V, RL=4 Ω, ID≈10 A, VGEN=4.5 V, Rg=1 Ω |
| Fall Time | 6 ns typ, 15 ns max; VDD=40 V, RL=4 Ω, ID≈10 A, VGEN=4.5 V, Rg=1 Ω |
| Continuous Source-Drain Diode Current | 52 A max; TC=25°C |
| Pulse Diode Forward Current | 40 A max; body diode characteristic |
| Body Diode Voltage | 0.85 V typ, 1.1 V max; IS=15 A, VGS=0 V |
| Body Diode Reverse Recovery Time | 30 ns typ, 60 ns max; IF=10 A, di/dt=100 A/µs, TJ=25°C |
| Body Diode Reverse Recovery Charge | 31 nC typ, 60 nC max; IF=10 A, di/dt=100 A/µs, TJ=25°C |
| Reverse Recovery Fall Time | 25 ns typ; IF=10 A, di/dt=100 A/µs, TJ=25°C |
| Reverse Recovery Rise Time | 5 ns typ; IF=10 A, di/dt=100 A/µs, TJ=25°C |
| Configuration | Dual; product summary |
| Ordering Part Number | SiZF4800LDT-T1-GE3; lead (Pb)-free and halogen-free ordering information |
| Datasheet Status | request_only |
Product Overview
The Vishay SIZF4800LDT is specified as a dual N-channel MOSFET for Power_Management applications. It uses a PowerPAIR 3 x 3FS package measuring 3.3 mm x 3.3 mm, providing a compact dual-MOSFET format for board-level power switching designs.
Its absolute maximum ratings include 80 V drain-source voltage and ±20 V gate-source voltage. Continuous drain current is rated at 36 A with TC=25°C and TJ=150°C, derating to 29 A at TC=70°C. For surface-mounted operation on a 1 in x 1 in FR4 board at t=10 s, continuous drain current is specified as 10 A at TA=25°C and 8 A at TA=70°C.
The device has low on-state resistance values of 0.019 Ω maximum at VGS=10 V, ID=10 A, and 0.0238 Ω maximum at VGS=4.5 V, ID=5 A. Gate-charge data includes 15 nC typical and 23 nC maximum at 10 V drive, with switching times characterized at both 10 V and 4.5 V gate drive conditions. Thermal and assembly data include 260°C soldering peak temperature and -55°C to +150°C junction and storage range.
Key Features
- Dual N-channel MOSFET configuration
- 80 V drain-source voltage rating
- ±20 V gate-source voltage rating
- 36 A continuous drain current at TC=25°C
- 0.019 Ω maximum RDS(on) at 10 V gate drive
- 23 nC maximum total gate charge at 10 V
- PowerPAIR 3 x 3FS, 3.3 mm package
- -55°C to +150°C junction and storage range
- 260°C soldering peak temperature
- 52 A source-drain diode current at TC=25°C
Typical Applications
- Power switching stages
- Dual MOSFET power rails
- 80 V power management circuits
- Low RDS(on) load switching
- Gate-driven switching designs
- Body-diode conduction paths
- Compact 3.3 mm board layouts
Procurement Notes
When requesting a quote for SIZF4800LDT, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What type of device is the SIZF4800LDT?
The SIZF4800LDT is a Vishay dual N-channel MOSFET in the Power_Management category. The extracted product information lists the package as PowerPAIR 3 x 3FS with 3.3 mm x 3.3 mm dimensions.
What voltage ratings are specified for SIZF4800LDT?
The datasheet facts specify an 80 V drain-source voltage absolute maximum rating and a ±20 V gate-source voltage absolute maximum rating at TA=25°C unless otherwise noted.
What are the main current ratings for this MOSFET?
Continuous drain current is specified as 36 A at TC=25°C and 29 A at TC=70°C, both with TJ=150°C. A 40 A pulsed drain current is also listed for t=100 µs.
What on-resistance values are given for SIZF4800LDT?
Drain-source on-state resistance is specified as 0.0160 Ω typical and 0.019 Ω maximum at VGS=10 V, ID=10 A. At VGS=4.5 V and ID=5 A, it is 0.0185 Ω typical and 0.0238 Ω maximum.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.