Specifications
| Type | Description |
|---|---|
| Part Number | SN65LVDS100 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | SOIC-8 4.90 mm x 3.91 mm; VSSOP-8 3.00 mm x 3.00 mm |
| Signaling rate | up to 2 Gbps; LVDS, PECL, or CML input repeated as LVDS or PECL output |
| Total jitter | <65 ps; feature summary |
| Part-to-part skew | 100 ps max; feature summary and VID=0.2 V specification |
| Receiver input threshold hysteresis | 25 mV over 0 V to 4 V input voltage range |
| Supply voltage operation | 3.3 V; feature summary |
| Integrated termination resistor | 110 ohm; SN65LVDT100 and SN65LVDT101 only |
| Output type | LVDS; SN65LVDS100 and SN65LVDT100 outputs per TIA/EIA-644-A |
| Output type | 3.3 V PECL compatible; SN65LVDS101 and SN65LVDT101 outputs |
| Differential transmission line impedance | 100 ohm nominal; driven by all devices |
| VBB reference voltage | typically VCC - 1.35 V; SN65LVDS100 and SN65LVDS101 for single-ended inputs, especially 3.3 V PECL |
| Operating free-air temperature | -40 to 85 °C; all devices characterized for operation |
| Orderable part output/termination/VBB | LVDS / no termination / VBB yes; SN65LVDS100D and SN65LVDS100DGK |
| Orderable part output/termination/VBB | LVDS / termination yes / VBB no; SN65LVDT100D and SN65LVDT100DGK |
| Orderable part output/termination/VBB | LVPECL / no termination / VBB yes; SN65LVDS101D and SN65LVDS101DGK |
| Orderable part output/termination/VBB | LVPECL / termination yes / VBB no; SN65LVDT101D and SN65LVDT101DGK |
| Pin A | Pin 2, differential non-inverting input; all variants |
| Pin B | Pin 3, differential inverting input; all variants |
| Pin Y | Pin 7, differential non-inverting output; all variants |
| Pin Z | Pin 6, differential inverting output; all variants |
| Pin VCC | Pin 8, supply voltage; all variants |
| Pin GND | Pin 5, ground; all variants |
| Pin VBB | Pin 4, voltage reference output; SN65LVDS100 and SN65LVDS101 only |
| Absolute maximum supply voltage range | -0.5 to 4 V over operating free-air temperature range |
| Absolute maximum VBB output current | -0.5 to 0.5 mA; VBB output |
| Absolute maximum I/O voltage range | 0 to 4.3 V; A, B, Y, Z pins |
| Absolute maximum differential voltage | 1 V; |VA - VB|, SN65LVDT100 and SN65LVDT101 only |
| HBM ESD rating | ±5000 V; pins 2, 3, 5, 6, 7; ANSI/ESDA/JEDEC JS-001 |
| HBM ESD rating | ±2000 V; all pins except 2, 3, 5, 6, 7; ANSI/ESDA/JEDEC JS-001 |
| CDM ESD rating | ±1500 V per JEDEC JESD22-C101 |
| Recommended supply voltage | 3.0 V min, 3.3 V nom, 3.6 V max; VCC |
| Differential input voltage magnitude | 0.1 to 1 V; SN65LVDS100 or SN65LVDS101 |
| Differential input voltage magnitude | 0.1 to 0.8 V; SN65LVDT100 or SN65LVDT101 |
| Input voltage range | 0 to 4 V; any combination of common-mode or input signals, VI |
| VBB output current | -400 to 12 µA; IO(VBB), algebraic convention used |
| Operating free-air temperature | -40 to 85 °C; recommended operating conditions, TA |
| Junction-to-ambient thermal resistance | 208 °C/W; D package, 8 pins |
| Junction-to-ambient thermal resistance | 263 °C/W; DGK package, 8 pins |
| Power dissipation rating | 151 mW; D package, TA <= 25 °C |
| Power dissipation rating | 377 mW; DGK package, TA <= 25 °C |
| Power dissipation rating | 192 mW; D package, TA <= 85 °C |
| Power dissipation rating | 481 mW; DGK package, TA <= 85 °C |
| Supply current | 25 mA typ, 30 mA max; SN65LVDx100, no load or input |
| Supply current | 50 mA typ, 61 mA max; SN65LVDx101, RL=50 ohm to 1 V, no input |
| Device power dissipation | 110 mW typ; SN65LVDx100, RL=100 ohm, no input |
| Device power dissipation | 116 mW typ, 142 mW max; SN65LVDx101, Y and Z to VCC - 2 V through 50 ohm, no input |
| Reference voltage output | VCC - 1.4 V min, VCC - 1.35 V typ, VCC - 1.3 V max; SN65LVDS100 or SN65LVDS101, IO=-400 µA or 12 µA |
| Positive-going differential input threshold | 100 mV max; SN65LVDS100 and SN65LVDS101 input characteristics, see Figure 30 and Table 1 |
| Negative-going differential input threshold | -100 mV min; SN65LVDS100 and SN65LVDS101 input characteristics, see Figure 30 and Table 1 |
| Input current | -20 to 20 µA; SN65LVDS100 and SN65LVDS101, VI=0 V or 2.4 V, second input at 1.2 V |
| Input current | 33 µA max; SN65LVDS100 and SN65LVDS101, VI=4 V, second input at 1.2 V |
| Power-off input current | -20 to 20 µA; SN65LVDS100 and SN65LVDS101, VCC=1.5 V, VI=0 V or 2.4 V, second input at 1.2 V |
| Power-off input current | 33 µA max; SN65LVDS100 and SN65LVDS101, VCC=1.5 V, VI=4 V, second input at 1.2 V |
| Input offset current | -6 to 6 µA; SN65LVDS100 and SN65LVDS101, |IIA-IIB|, VIA=VIB, 0 <= VIA <= 4 V |
| Small-signal input capacitance to GND | 0.6 pF typ; SN65LVDS100 and SN65LVDS101, VI=1.2 V |
| Positive-going differential input threshold | 100 mV max; SN65LVDT100 and SN65LVDT101 input characteristics, see Figure 30 and Table 1 |
| Negative-going differential input threshold | -100 mV min; SN65LVDT100 and SN65LVDT101 input characteristics, see Figure 30 and Table 1 |
| Input current | -40 to 40 µA; SN65LVDT100 and SN65LVDT101, VI=0 V or 2.4 V, other input open |
| Input current | 66 µA max; SN65LVDT100 and SN65LVDT101, VI=4 V, other input open |
| Power-off input current | -40 to 40 µA; SN65LVDT100 and SN65LVDT101, VCC=1.5 V, VI=0 V or 2.4 V, other input open |
| Power-off input current | 66 µA max; SN65LVDT100 and SN65LVDT101, VCC=1.5 V, VI=4 V, other input open |
| Differential input resistance | 90 ohm min, 110 ohm typ, 132 ohm max; SN65LVDT100 and SN65LVDT101, VID=300 mV or 500 mV, VIC=0 V or 2.4 V |
| Differential input resistance | 90 ohm min, 110 ohm typ, 132 ohm max; SN65LVDT100 and SN65LVDT101, VCC=0 V, VID=300 mV or 500 mV, VIC=0 V or 2.4 V |
| Small-signal differential input capacitance | 0.6 pF typ; SN65LVDT100 and SN65LVDT101, VI=1.2 V |
| LVDS differential output voltage magnitude | 247 mV min, 340 mV typ, 454 mV max; SN65LVDS100 and SN65LVDT100, see Figure 31 |
| Change in LVDS differential output voltage magnitude | -50 to 50 mV; SN65LVDS100 and SN65LVDT100, between logic states, see Figure 31 |
| LVDS steady-state common-mode output voltage | 1.125 to 1.375 V; SN65LVDS100 and SN65LVDT100 |
| Change in LVDS steady-state common-mode output voltage | -50 to 50 mV; SN65LVDS100 and SN65LVDT100, between logic states, see Figure 32 |
| LVDS peak-to-peak common-mode output voltage | 50 mV typ, 150 mV max; SN65LVDS100 and SN65LVDT100 |
| Short-circuit output current | -24 to 24 mA; SN65LVDS100 and SN65LVDT100, VO(Y) or VO(Z)=0 V |
| Differential short-circuit output current | -12 to 12 mA; SN65LVDS100 and SN65LVDT100, VOD=0 V |
| PECL high-level output voltage | VCC - 1.25 V min, VCC - 1.02 V typ, VCC - 0.9 V max; SN65LVDS101 and SN65LVDT101, 50 ohm to VCC - 2 V, see Figure 39 |
| PECL high-level output voltage | 2055 mV min, 2280 mV typ, 2405 mV max; SN65LVDS101 and SN65LVDT101, VCC=3.3 V, 50 ohm load to 2.3 V |
| PECL low-level output voltage | VCC - 1.83 V min, VCC - 1.61 V typ, VCC - 1.53 V max; SN65LVDS101 and SN65LVDT101, 50 ohm to VCC - 2 V, see Figure 39 |
| PECL low-level output voltage | 1475 mV min, 1690 mV typ, 1775 mV max; SN65LVDS101 and SN65LVDT101, VCC=3.3 V, 50 ohm load to 2.3 V |
| PECL differential output voltage magnitude | 475 mV min, 575 mV typ, 750 mV max; SN65LVDS101 and SN65LVDT101, 50 ohm load to VCC - 2 V, see Figure 39 |
| Propagation delay low-to-high | 300 ps min, 470 ps typ, 800 ps max; SN65LVDx100, see Figure 33 |
| Propagation delay low-to-high | 400 ps min, 630 ps typ, 900 ps max; SN65LVDx101, see Figure 33 |
| Propagation delay high-to-low | 300 ps min, 470 ps typ, 800 ps max; SN65LVDx100, see Figure 33 |
| Propagation delay high-to-low | 400 ps min, 630 ps typ, 900 ps max; SN65LVDx101, see Figure 33 |
| Differential output signal rise time | 220 ps typ; 20% to 80%, see Figure 33 |
| Differential output signal fall time | 220 ps typ; 20% to 80%, see Figure 33 |
| Pulse skew | 5 ps typ, 50 ps max; |tPHL - tPLH| of any output of a single device |
| Part-to-part skew | 100 ps max; VID=0.2 V, see Figure 33; same supply, temperature, package, and test circuits |
| RMS period jitter | 1 ps typ, 3.7 ps max; 1 GHz 50% duty-cycle square-wave input |
| Peak cycle-to-cycle jitter | 6 ps typ, 23 ps max; VID=200 mV, VIC=1.2 V, see Figure 34 |
| Peak-to-peak jitter | 28 ps typ, 65 ps max; 2 GHz PRBS, 2^23 - 1 run length, VID=200 mV, VIC=1.2 V, see Figure 34 |
| Peak-to-peak deterministic jitter | 17 ps typ, 48 ps max; 2 GHz PRBS, 2^7 - 1 run length, VID=200 mV, VIC=1.2 V, see Figure 34 |
| Datasheet Status | request_only |
Product Overview
The SN65LVDS100 is a Texas Instruments Signal_Chain differential translator/repeater. It accepts LVDS, PECL, or CML inputs and repeats them as an LVDS output, supporting signaling rates up to 2 Gbps. The SN65LVDS100 and SN65LVDT100 output format follows TIA/EIA-644-A LVDS behavior and drives a nominal 100 ohm differential transmission line.
For the SN65LVDS100 orderable options, the device provides LVDS output, no integrated termination, and a VBB reference output. VBB is typically VCC - 1.35 V and is intended for single-ended inputs, especially 3.3 V PECL. Pin functions include A on pin 2, B on pin 3, VBB on pin 4, GND on pin 5, Z on pin 6, Y on pin 7, and VCC on pin 8.
The device operates from a 3.3 V supply, with recommended VCC from 3.0 V to 3.6 V, and is characterized from -40 to 85 °C. Package options include SOIC-8 and VSSOP-8. Timing specifications include 470 ps typical propagation delay for SN65LVDx100 devices, 220 ps typical differential rise and fall times, and 65 ps maximum peak-to-peak jitter under the specified 2 GHz PRBS condition.
Key Features
- Repeats LVDS, PECL, or CML inputs up to 2 Gbps
- LVDS output per TIA/EIA-644-A for SN65LVDS100
- 3.0 V to 3.6 V recommended VCC range
- 25 mV receiver input threshold hysteresis over 0 V to 4 V
- 100 ps maximum part-to-part skew under specified conditions
- 65 ps maximum peak-to-peak jitter with 2 GHz PRBS input
- VBB reference output typically equals VCC minus 1.35 V
- SOIC-8 and VSSOP-8 package options available
- LVDS differential output magnitude is 247 mV to 454 mV
- Characterized over -40 to 85 °C free-air temperature
Typical Applications
- LVDS signal repeating
- PECL input translation
- CML input conversion
- Single-ended PECL input biasing
- 100 ohm differential line driving
- 2 Gbps differential links
Procurement Notes
When requesting a quote for SN65LVDS100, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What output type does the SN65LVDS100 provide?
The SN65LVDS100 provides an LVDS output. The extracted datasheet facts state that SN65LVDS100 and SN65LVDT100 outputs are per TIA/EIA-644-A, and that the SN65LVDS100 orderable parts use LVDS output with no integrated termination and VBB available.
What supply range is recommended for SN65LVDS100 operation?
The recommended VCC range is 3.0 V minimum, 3.3 V nominal, and 3.6 V maximum. The feature summary also lists 3.3 V supply voltage operation, and the device is characterized for operation from -40 to 85 °C free-air temperature.
How fast can the SN65LVDS100 repeat differential signals?
The signaling rate is specified up to 2 Gbps when LVDS, PECL, or CML input is repeated as an LVDS or PECL output. Timing facts also include 470 ps typical propagation delay for SN65LVDx100 and 220 ps typical differential rise and fall times.
Which pins are used for SN65LVDS100 differential input and output?
For all variants, A is pin 2 and B is pin 3 for the differential input. The differential output uses Y on pin 7 and Z on pin 6. VCC is pin 8, GND is pin 5, and VBB is pin 4 on SN65LVDS100.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 25, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.