Specifications
| Type | Description |
|---|---|
| Part Number | SN65LVDS101 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | SOIC-8 4.90 mm x 3.91 mm; VSSOP-8 3.00 mm x 3.00 mm |
| Maximum signaling rate | >=2 Gbps; condition: device feature rating |
| Output logic standard | LVPECL / 3.3-V PECL compatible; condition: SN65LVDS101 outputs |
| Input compatibility | LVDS, LVPECL, CML; condition: receiver input signal compatibility |
| Supply voltage | 3.0 V min, 3.3 V nom, 3.6 V max; condition: recommended operating conditions |
| Operating free-air temperature | -40°C to 85°C; condition: recommended operating conditions |
| Differential input voltage magnitude | 0.1 V min, 1.0 V max; condition: SN65LVDS101 recommended operating conditions |
| Input voltage range | 0 V min, 4 V max; condition: any combination of common-mode or input signals |
| VBB output current | -400 µA min, 12 µA max; condition: recommended operating conditions |
| Absolute maximum supply voltage | -0.5 V to 4 V; condition: over operating free-air temperature range |
| Absolute maximum I/O voltage range | 0 V to 4.3 V; condition: A, B, Y, Z pins |
| ESD rating, HBM pins 2, 3, 5, 6, 7 | ±5000 V |
| ESD rating, HBM all other pins | ±2000 V |
| ESD rating, CDM | ±1500 V; condition: per JESD22-C101 |
| Junction-to-ambient thermal resistance, D package | 208°C/W; condition: 8 pins |
| Junction-to-ambient thermal resistance, DGK package | 263°C/W; condition: 8 pins |
| Supply current | 50 mA typ, 61 mA max; condition: SN65LVDS101, RL=50 Ω to 1 V, no input |
| Device power dissipation | 116 mW typ, 142 mW max; condition: SN65LVDS101, Y and Z to VCC-2 V through 50 Ω, no input |
| Reference voltage output | VCC-1.4 V min, VCC-1.35 V typ, VCC-1.3 V max; condition: SN65LVDS101, IO=-400 µA or 12 µA |
| Positive-going differential input voltage threshold | 100 mV max; condition: SN65LVDS101 input characteristics |
| Negative-going differential input voltage threshold | -100 mV min; condition: SN65LVDS101 input characteristics |
| Input current | -20 µA min, 20 µA max; condition: VI=0 V or 2.4 V, second input at 1.2 V |
| Input current at 4 V | 33 µA max; condition: VI=4 V, second input at 1.2 V |
| Power-off input current | -20 µA min, 20 µA max; condition: VCC=1.5 V, VI=0 V or 2.4 V, second input at 1.2 V |
| Input offset current | -6 µA min, 6 µA max; condition: VIA=VIB, 0≤VIA≤4 V |
| Small-signal input capacitance to GND | 0.6 pF typ; condition: VI=1.2 V |
| High-level output voltage | VCC-1.25 V min, VCC-1.02 V typ, VCC-0.9 V max; condition: SN65LVDS101, 50 Ω to VCC-2 V |
| High-level output voltage at VCC=3.3 V | 2055 mV min, 2280 mV typ, 2405 mV max; condition: 50-Ω load to 2.3 V |
| Low-level output voltage | VCC-1.83 V min, VCC-1.61 V typ, VCC-1.53 V max; condition: SN65LVDS101, 50 Ω to VCC-2 V |
| Low-level output voltage at VCC=3.3 V | 1475 mV min, 1690 mV typ, 1775 mV max; condition: 50-Ω load to 2.3 V |
| Differential output voltage magnitude | 475 mV min, 575 mV typ, 750 mV max; condition: SN65LVDS101, 50-Ω load to VCC-2 V |
| Propagation delay low-to-high | 400 ps min, 630 ps typ, 900 ps max; condition: SN65LVDS101 |
| Propagation delay high-to-low | 400 ps min, 630 ps typ, 900 ps max; condition: SN65LVDS101 |
| Differential output signal rise time | 220 ps typ; condition: 20% to 80% |
| Differential output signal fall time | 220 ps typ; condition: 20% to 80% |
| Pulse skew | 5 ps typ, 50 ps max; condition: |tPHL - tPLH| |
| Part-to-part skew | 100 ps max; condition: VID=0.2 V |
| RMS period jitter | 1 ps typ, 3.7 ps max; condition: 1 GHz 50% duty-cycle square-wave input |
| Peak cycle-to-cycle jitter | 6 ps typ, 23 ps max; condition: VID=200 mV, VIC=1.2 V |
| Peak-to-peak jitter | 28 ps typ, 65 ps max; condition: 2 GHz PRBS, 2^23-1 run length, VID=200 mV, VIC=1.2 V |
| Peak-to-peak deterministic jitter | 17 ps typ, 48 ps max; condition: 2 GHz PRBS, 2^7-1 run length, VID=200 mV, VIC=1.2 V |
| Datasheet Status | request_only |
Product Overview
The SN65LVDS101 is a Texas Instruments Signal_Chain differential translator/repeater intended for high-speed differential signaling interfaces. Its receiver input compatibility covers LVDS, LVPECL, and CML, while the outputs are LVPECL / 3.3-V PECL compatible. The extracted datasheet facts rate the device for a maximum signaling rate of at least 2 Gbps.
Recommended operation is based on a 3.0 V to 3.6 V supply, with 3.3 V nominal operation, and a -40°C to 85°C free-air temperature range. Differential input voltage magnitude is specified from 0.1 V to 1.0 V, and the input voltage range supports 0 V to 4 V for common-mode or input signal combinations.
Package options are SOIC-8 at 4.90 mm x 3.91 mm and VSSOP-8 at 3.00 mm x 3.00 mm. Thermal resistance is specified as 208°C/W for the D 8-pin package and 263°C/W for the DGK 8-pin package. Applications should account for 50 mA typical supply current, 116 mW typical device dissipation, and the specified LVPECL output levels, propagation delay, skew, and jitter limits.
Key Features
- At least 2 Gbps maximum signaling rate
- Accepts LVDS, LVPECL, and CML receiver inputs
- LVPECL / 3.3-V PECL-compatible output stage
- 3.0 V to 3.6 V recommended supply range
- -40°C to 85°C operating free-air temperature
- 0.1 V to 1.0 V differential input magnitude
- 400 ps to 900 ps low-to-high propagation delay
- 400 ps to 900 ps high-to-low propagation delay
- 220 ps typical differential output rise and fall times
- 1 ps typical RMS period jitter at 1 GHz
- SOIC-8 and VSSOP-8 package options
Typical Applications
- LVDS to LVPECL signal translation
- CML input signal repeating
- 3.3-V PECL-compatible output interfaces
- 2 Gbps differential signal paths
- Clock distribution with low RMS jitter
- High-speed Signal_Chain interconnects
- Differential input receiver adaptation
Procurement Notes
When requesting a quote for SN65LVDS101, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the SN65LVDS101?
The SN65LVDS101 is a Texas Instruments differential translator/repeater in the Signal_Chain category. The extracted datasheet facts identify LVDS, LVPECL, and CML input compatibility and LVPECL / 3.3-V PECL-compatible outputs.
What supply and temperature range does SN65LVDS101 support?
Recommended operation is specified from 3.0 V minimum to 3.6 V maximum, with 3.3 V nominal supply. The operating free-air temperature range is -40°C to 85°C.
What packages are listed for SN65LVDS101?
The package information lists SOIC-8 measuring 4.90 mm x 3.91 mm and VSSOP-8 measuring 3.00 mm x 3.00 mm. Thermal resistance is 208°C/W for the D package and 263°C/W for the DGK package.
What timing performance is specified for this translator repeater?
The extracted facts specify 400 ps to 900 ps propagation delay for both low-to-high and high-to-low transitions, 220 ps typical differential output rise and fall times, 5 ps typical pulse skew, and 100 ps maximum part-to-part skew.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 25, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.