Specifications
| Type | Description |
|---|---|
| Part Number | SN65LVDS104 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 16-pin SOIC (D), 9.90 mm x 3.91 mm; 16-pin TSSOP (PW), 5.00 mm x 4.40 mm |
| Input Type | 1 LVDS input; condition: SN65LVDS104 device selection guide; source page: 3 |
| Output Type | 4 LVDS outputs; condition: SN65LVDS104 device selection guide; source page: 3 |
| Data Signaling Rate | 400 Mbps typical; condition: Feature list; source page: 1 |
| Clock Frequency | 400 MHz typical; condition: Feature list; source page: 1 |
| Supply Voltage | 3.0 V min, 3.3 V nom, 3.6 V max; condition: Recommended operating conditions; source page: 4 |
| Operating Free-Air Temperature | -40 deg C min, 85 deg C max; condition: Recommended operating conditions; source page: 4 |
| Positive-Going Differential Input Voltage Threshold | 100 mV max; condition: See Figure 13 and Table 1; source page: 5 |
| Negative-Going Differential Input Voltage Threshold | -100 mV min; condition: See Figure 13 and Table 1; source page: 5 |
| Differential Output Voltage Magnitude | 247 mV min, 340 mV typ, 454 mV max; condition: RL = 100 ohm, VID = +/-100 mV; see Figure 13 and Figure 14; source page: 5 |
| Change in Differential Output Voltage Magnitude Between Logic States | -50 mV min, 50 mV max; condition: RL = 100 ohm, VID = +/-100 mV; see Figure 13 and Figure 14; source page: 5 |
| Steady-State Common-Mode Output Voltage | 1.125 V min, 1.375 V max; condition: See Figure 15; source page: 5 |
| Change in Steady-State Common-Mode Output Voltage Between Logic States | -50 mV min, 50 mV max; condition: See Figure 15; source page: 5 |
| Peak-to-Peak Common-Mode Output Voltage | 25 mV typ, 150 mV max; condition: See Figure 15; source page: 5 |
| Supply Current Enabled | 23 mA typ, 35 mA max; condition: Enabled, RL = 100 ohm; source page: 5 |
| Supply Current Disabled | 3 mA typ, 8 mA max; condition: Disabled; source page: 5 |
| Input Current A or B | -20 uA min, -11 uA typ, -2 uA max; condition: VI = 0 V; source page: 5 |
| Input Current A or B | -3 uA min, -1.2 uA typ; condition: VI = 2.4 V; source page: 5 |
| Power-Off Input Current | 20 uA max; condition: VCC = 1.5 V, VI = 2.4 V; source page: 5 |
| High-Level Input Current Enables | 20 uA max; condition: VIH = 2 V; source page: 5 |
| Low-Level Input Current Enables | 10 uA max; condition: VIL = 0.8 V; source page: 5 |
| Short-Circuit Output Current | +/-10 mA max; condition: VOY or VOZ = 0 V; source page: 5 |
| Short-Circuit Output Current | +/-10 mA max; condition: VOD = 0 V; source page: 5 |
| High-Impedance Output Current | +/-1 uA max; condition: VO = 0 V or 2.4 V; source page: 5 |
| Power-Off Output Current | +/-1 uA max; condition: VCC = 1.5 V, VO = 2.4 V; source page: 5 |
| Input Capacitance A or B | 3 pF typ; condition: VI = 0.4sin(4E6*pi*t) + 0.5 V; source page: 5 |
| Output Capacitance Y or Z | 9.4 pF typ; condition: VI = 0.4sin(4E6*pi*t) + 0.5 V, disabled; source page: 5 |
| Propagation Delay Low-to-High Output | 2.4 ns min, 3.2 ns typ, 4.2 ns max; condition: RL = 100 ohm, CL = 10 pF; see Figure 16; source page: 6 |
| Propagation Delay High-to-Low Output | 2.2 ns min, 3.1 ns typ, 4.2 ns max; condition: RL = 100 ohm, CL = 10 pF; see Figure 16; source page: 6 |
| Differential Output Signal Rise Time | 0.3 ns min, 0.8 ns typ, 1.2 ns max; condition: RL = 100 ohm, CL = 10 pF; see Figure 16; source page: 6 |
| Differential Output Signal Fall Time | 0.3 ns min, 0.8 ns typ, 1.2 ns max; condition: RL = 100 ohm, CL = 10 pF; see Figure 16; source page: 6 |
| Pulse Skew | 150 ps typ, 500 ps max; condition: |tPHL - tPLH|, RL = 100 ohm, CL = 10 pF; see Figure 16; source page: 6 |
| Channel-to-Channel Output Skew | 20 ps typ, 100 ps max; condition: RL = 100 ohm, CL = 10 pF; see Figure 16; source page: 6 |
| Part-to-Part Skew | 1.5 ns max; condition: Same supply voltages, same temperature, identical packages and test circuits; source page: 6 |
| Propagation Delay High-Impedance-to-High Output | 7.2 ns typ, 15 ns max; condition: See Figure 17; source page: 6 |
| Propagation Delay High-Impedance-to-Low Output | 8.4 ns typ, 15 ns max; condition: See Figure 17; source page: 6 |
| Propagation Delay High-to-High-Impedance Output | 3.6 ns typ, 15 ns max; condition: See Figure 17; source page: 6 |
| Propagation Delay Low-to-High-Impedance Output | 6 ns typ, 15 ns max; condition: See Figure 17; source page: 6 |
| Absolute Maximum Supply Voltage | -0.5 V min, 4 V max; condition: Over operating free-air temperature range; source page: 4 |
| Absolute Maximum A, B, Y, or Z Voltage | -0.5 V min, 4 V max; condition: Over operating free-air temperature range; source page: 4 |
| Storage Temperature | -65 deg C min, 150 deg C max; condition: Absolute maximum ratings; source page: 4 |
| JEDEC HBM ESD Rating | +/-12000 V; condition: ANSI/ESDA/JEDEC JS-001; source page: 4 |
| JEDEC CDM ESD Rating | +/-1500 V; condition: JEDEC JESD22-C101; source page: 4 |
| Bus-Pin ESD Rating | 16000 V Class 3A, 400 V Class 3B; condition: MIL-STD-883C Method 3015.7; A, B, Y, Z, and GND pins; source page: 4 |
| Datasheet Status | request_only |
Product Overview
The SN65LVDS104 is a Texas Instruments Signal_Chain 4-port LVDS repeater with 1 LVDS input and 4 LVDS outputs. It is specified for LVDS signal repetition and distribution where one differential input must drive multiple LVDS output channels.
The device operates from a 3.0 V to 3.6 V supply with a 3.3 V nominal value and supports -40 deg C to 85 deg C free-air operation. Typical signaling capability is 400 Mbps data rate or 400 MHz clock frequency. Input threshold limits are 100 mV maximum positive-going differential threshold and -100 mV minimum negative-going differential threshold.
Package options include 16-pin SOIC (D), 9.90 mm x 3.91 mm, and 16-pin TSSOP (PW), 5.00 mm x 4.40 mm. Output timing specifications include 3.2 ns typical low-to-high propagation delay, 3.1 ns typical high-to-low propagation delay, 0.8 ns typical rise and fall times, 150 ps typical pulse skew, and 20 ps typical channel-to-channel output skew under the listed 100 ohm and 10 pF test conditions.
Key Features
- 1 LVDS input and 4 LVDS outputs
- 400 Mbps typical data signaling rate
- 400 MHz typical clock frequency
- 3.0 V to 3.6 V supply range
- -40 deg C to 85 deg C free-air operation
- 247 mV to 454 mV differential output magnitude
- 1.125 V to 1.375 V common-mode output voltage
- 3.2 ns typical low-to-high propagation delay
- 20 ps typical channel-to-channel output skew
- 16-pin SOIC and 16-pin TSSOP package options
Typical Applications
- LVDS signal repetition
- One-to-four LVDS distribution
- LVDS clock distribution
- 400 Mbps differential data paths
- 400 MHz clock fanout
- Signal_Chain interface routing
- Multi-output LVDS buffering
Procurement Notes
When requesting a quote for SN65LVDS104, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the SN65LVDS104?
The SN65LVDS104 is a Texas Instruments 4-port LVDS repeater in the Signal_Chain category. The extracted device selection facts specify 1 LVDS input and 4 LVDS outputs.
What supply range is specified for SN65LVDS104 operation?
The recommended operating supply voltage is 3.0 V minimum, 3.3 V nominal, and 3.6 V maximum. The recommended operating free-air temperature range is -40 deg C to 85 deg C.
What data and clock rates are listed for the SN65LVDS104?
The feature list gives a 400 Mbps typical data signaling rate and a 400 MHz typical clock frequency for the SN65LVDS104.
What package options are listed for the SN65LVDS104?
The listed package options are 16-pin SOIC (D), measuring 9.90 mm x 3.91 mm, and 16-pin TSSOP (PW), measuring 5.00 mm x 4.40 mm.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 25, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.