Specifications
| Type | Description |
|---|---|
| Part Number | SN65LVDS108 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package Case | 38-pin DBT thin shrink small-outline package, 20-mil terminal pitch |
| Configuration | 1 differential LVDS line receiver to 8 differential LVDS line drivers |
| Data Signaling Rate | 400 Mbps typical |
| Clock Frequency | 400 MHz typical |
| Typical Differential Output Voltage | 350 mV, 100-ohm load |
| Operating Free-Air Temperature | -40 to 85 °C, recommended operating range |
| Supply Voltage | 3.0 min, 3.3 nom, 3.6 max V |
| High-Level Input Voltage | 2.0 V min, enable inputs |
| Low-Level Input Voltage | 0.8 V max, enable inputs |
| Bus Terminal Voltage | 0 to VCC - 0.8 V, any bus terminal separately or common-mode |
| Positive-Going Differential Input Threshold | 100 mV max |
| Negative-Going Differential Input Threshold | -100 mV min |
| Differential Output Voltage Magnitude | 247 min, 340 typ, 454 max mV, RL=100 ohm, VID=-100 mV |
| Differential Output Voltage Change Between Logic States | -50 to 50 mV, RL=100 ohm, VID=-100 mV |
| Steady-State Common-Mode Output Voltage | 1.125 min, 1.375 max V |
| Common-Mode Output Voltage Change | -50 to 50 mV, between logic states |
| Peak-to-Peak Common-Mode Output Voltage | 50 typ, 150 max mV |
| Supply Current Enabled | 62 typ, 85 max mA, enabled, RL=100 ohm |
| Supply Current Disabled | 8 typ, 12 max mA, disabled outputs |
| Input Current | 2 typ, 20 max uA, A or B inputs, VI=0 V |
| Input Current | 1.2 typ uA, A or B inputs, VI=2.4 V |
| Power-Off Input Current | 20 max uA, A or B inputs, VCC=1.5 V, VI=2.4 V |
| High-Level Enable Input Current | -20 max uA, VIH=2 V |
| Low-Level Enable Input Current | -10 max uA, VIL=0.8 V |
| Short-Circuit Output Current | -24 mA, VOY or VOZ=0 V |
| Short-Circuit Output Current | -12 mA, VOD=0 V |
| High-Impedance Output Current | -1 max uA, VO=0 V or VCC |
| Power-Off Output Current | -1 max uA, VCC=1.5 V, VO=3.6 V |
| Input Capacitance | 5 pF, A or B inputs |
| Output Capacitance | 9.4 pF, Y or Z outputs disabled |
| Low-to-High Propagation Delay | 1.6 min, 2.8 typ, 4.5 max ns, RL=100 ohm, CL=10 pF |
| High-to-Low Propagation Delay | 1.6 min, 2.8 typ, 4.5 max ns, RL=100 ohm, CL=10 pF |
| Differential Output Rise Time | 0.3 min, 0.8 typ, 1.2 max ns, RL=100 ohm, CL=10 pF |
| Differential Output Fall Time | 0.3 min, 0.8 typ, 1.2 max ns, RL=100 ohm, CL=10 pF |
| Pulse Skew | 150 typ, 500 max ps |
| Output Skew | 300 max ps |
| Part-to-Part Skew | 1.5 max ns, same supply voltage, temperature, package, and test circuits |
| Enable Delay High-Impedance to High | 5.7 typ, 15 max ns |
| Enable Delay High-Impedance to Low | 7.7 typ, 15 max ns |
| Disable Delay High to High-Impedance | 3.2 typ, 15 max ns |
| Disable Delay Low to High-Impedance | 3.2 typ, 15 max ns |
| Datasheet Status | request_only |
Product Overview
The Texas Instruments SN65LVDS108 is an 8-port LVDS repeater for Signal_Chain designs that need one received LVDS differential input distributed to multiple LVDS differential outputs. Its device configuration is 1 differential LVDS line receiver driving 8 differential LVDS line drivers, supporting typical 400 Mbps data signaling and typical 400 MHz clock operation.
Recommended operation uses a 3.0 V minimum, 3.3 V nominal, and 3.6 V maximum supply. The operating free-air temperature range is -40 to 85 °C. Differential output voltage is specified at 350 mV typical with a 100-ohm load, with detailed output magnitude of 247 mV minimum, 340 mV typical, and 454 mV maximum under RL=100 ohm and VID=-100 mV.
The device is supplied in a 38-pin DBT thin shrink small-outline package with 20-mil terminal pitch. Timing parameters include 2.8 ns typical low-to-high and high-to-low propagation delay, 0.8 ns typical differential output rise and fall times, 500 ps maximum pulse skew, and 300 ps maximum output skew for LVDS distribution applications.
Key Features
- 1 differential LVDS receiver fans out to 8 LVDS drivers
- 400 Mbps typical data signaling rate
- 400 MHz typical clock operation
- 350 mV typical differential output into 100-ohm load
- 3.0 V to 3.6 V recommended supply range
- -40 to 85 °C operating free-air temperature
- 2.8 ns typical propagation delay with 10 pF load
- 500 ps maximum pulse skew, 300 ps maximum output skew
- 38-pin DBT package with 20-mil terminal pitch
Typical Applications
- LVDS clock fanout
- Differential data distribution
- Multi-output signal buffering
- Backplane signal distribution
- Point-to-point LVDS expansion
- High-speed board-level interconnects
- Repeated LVDS line driving
Procurement Notes
When requesting a quote for SN65LVDS108, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What is the SN65LVDS108 functional configuration?
The SN65LVDS108 is configured as 1 differential LVDS line receiver connected to 8 differential LVDS line drivers, making it an 8-port LVDS repeater for distributing one differential input signal to multiple LVDS outputs.
What data rate and clock frequency are specified?
The extracted datasheet facts specify a typical data signaling rate of 400 Mbps and typical clock operation at 400 MHz for the Texas Instruments SN65LVDS108.
What supply voltage range does SN65LVDS108 use?
Recommended operating conditions list the supply voltage as 3.0 V minimum, 3.3 V nominal, and 3.6 V maximum. Enable input thresholds are 2.0 V minimum for high level and 0.8 V maximum for low level.
What package is used for this LVDS repeater?
The SN65LVDS108 is supplied in a 38-pin DBT thin shrink small-outline package with 20-mil terminal pitch, according to the extracted package-case information.
What propagation delay and skew values are listed?
With RL=100 ohm and CL=10 pF, low-to-high and high-to-low propagation delays are both 1.6 ns minimum, 2.8 ns typical, and 4.5 ns maximum. Pulse skew is 150 ps typical and 500 ps maximum.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 25, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.