Specifications
| Type | Description |
|---|---|
| Part Number | SN65LVDS93 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package Case | DGG 56-pin thin shrink small-outline package, 20 mil terminal pitch |
| Data Channel Compression | 28:4; LVTTL parallel inputs serialized to LVDS outputs |
| Maximum Throughput | 1.904 Gbit/s; at maximum input clock frequency |
| Input Data Channels | 28 data channels plus clock; low-voltage TTL inputs |
| Output Data Channels | 4 data channels plus clock; low-voltage differential outputs |
| Input Clock Frequency Range | 20-68 MHz; PLL phase-lock input frequency range |
| Clock Multiplication | 7x; CLKIN multiplied by clock synthesizer/PLL |
| Supply Voltage | 3.0 min, 3.3 nom, 3.6 max V; recommended operating condition |
| Absolute Maximum Supply Voltage | -0.5 to 4 V; over operating free-air temperature range |
| Input Voltage Range | -0.5 to 5.5 V; absolute maximum rating at any input terminal |
| Output Voltage Range | -0.5 to VCC + 0.5 V; absolute maximum rating at any output terminal |
| High-Level Input Voltage | 2 V min; recommended operating condition |
| Low-Level Input Voltage | 0.8 V max; recommended operating condition |
| Differential Load Impedance | 90 min, 132 max ohm; recommended operating condition |
| Operating Free-Air Temperature | -40 to 85 °C; recommended operating condition and characterized range |
| Storage Temperature | -65 to 150 °C; absolute maximum rating |
| Lead Temperature | 260 °C; 1.6 mm from case for 10 seconds |
| DGG Package Power Rating at TA <= 25°C | 1377 mW |
| DGG Package Derating Factor | 11 mW/°C; above TA = 25°C |
| DGG Package Power Rating at TA = 70°C | 882 mW |
| DGG Package Power Rating at TA = 85°C | 717 mW |
| Input Voltage Threshold | 1.4 V; over recommended operating free-air temperature range |
| Differential Steady-State Output Voltage Magnitude | 247 min, 454 max mV; RL = 100 ohm |
| Differential Output Voltage Change Between Binary States | 50 mV max; RL = 100 ohm |
| Steady-State Common-Mode Output Voltage | 1.125 min, 1.375 max V |
| Peak-to-Peak Common-Mode Output Voltage | 150 mV max; over recommended operating free-air temperature range |
| High-Level Input Current | 20 uA max; VIH = VCC |
| Low-Level Input Current | ±10 uA max; VIL = 0 V |
| Short-Circuit Output Current at VOY = 0 V | ±24 mA max |
| Short-Circuit Output Current at VOD = 0 V | ±12 mA max |
| High-Impedance State Output Current | ±20 uA max; VO = 0 V to VCC |
| Quiescent Current | 350 uA max; disabled, all inputs at GND |
| Average Supply Current | 95 typ, 120 max mA; enabled, RL = 100 ohm at 5 places, worst-case pattern, tc = 15.38 ns |
| Input Capacitance | 3 pF typ; VCC = 3.3 V, TA = 25°C |
| Input Clock Period | 14.7 min, 50 max ns; timing requirement |
| High-Level Input Clock Pulse Width | 0.4tc min, 0.6tc max ns; timing requirement |
| Input Signal Transition Time | 5 ns max; timing requirement |
| Data Setup Time | 3 ns min; D0 through D27 before CLKIN rising or falling edge |
| Data Hold Time | 1.5 ns min; D0 through D27 after CLKIN falling or rising edge |
| Delay CLKOUT Rising to Serial Bit Position 0 | -0.20 min, 0 typ, 0.20 max ns; tc = 15.38 ns ±0.2%, input clock jitter <50 ps |
| Output Skew | -0.20 min, 0.20 max ns; tc = 15.38 ns ±0.2%, input clock jitter <50 ps |
| Delay CLKIN to CLKOUT | 4.2 ns max; CLKIN falling or rising edge to CLKOUT rising, tc = 15.38 ns ±0.2%, input clock jitter <50 ps |
| Output Clock Period | tc ps; switching characteristic |
| Output Clock Cycle-to-Cycle Jitter at 500 kHz Modulation | ±80 ps; tc = 15.38 ns + 0.75 sin(2π 500E3t) ±0.05 ns |
| Output Clock Cycle-to-Cycle Jitter at 3 MHz Modulation | ±300 ns; tc = 15.38 ns + 0.75 sin(2π 3E6t) ±0.05 ns |
| Differential Output Voltage Transition Time | 260 min, 700 typ, 1500 max ps; tr or tf |
| Enable Time | 1 ms max; SHTDN rising to phase lock, Yn valid |
| Disable Time | 250 ns max; SHTDN falling to off-state, CLKOUT low |
| Shutdown Function | Active low; SHTDN inhibits clock, shuts off LVDS drivers, and clears internal registers low |
| Clock Edge Select | CLKSEL high selects rising edge, CLKSEL low selects falling edge; input data capture clock edge selection |
| Datasheet Status | request_only |
Product Overview
Clocking is based on a PLL and clock synthesizer that multiplies CLKIN by 7x. The PLL phase-lock input frequency range is 20-68 MHz, and maximum throughput is specified as 1.904 Gbit/s at the maximum input clock frequency. Data capture can be selected by CLKSEL, with high selecting the rising edge and low selecting the falling edge.
The device operates from a recommended 3.0 to 3.6 V supply, with 3.3 V nominal operation, and is characterized across -40 to 85 °C free-air temperature. It is supplied in a DGG 56-pin thin shrink small-outline package with 20 mil terminal pitch. Assembly-related ratings include 260 °C lead temperature at 1.6 mm from the case for 10 seconds.
Interface parameters include 2 V minimum high-level input voltage, 0.8 V maximum low-level input voltage, 247 to 454 mV differential steady-state output voltage magnitude into 100 ohm, and 1.125 to 1.375 V steady-state common-mode output voltage. The active-low shutdown input inhibits the clock, shuts off LVDS drivers, and clears internal registers low.
Key Features
- 28:4 LVTTL-to-LVDS data channel compression
- 1.904 Gbit/s maximum throughput at maximum input clock
- 28 low-voltage TTL data channels plus clock input
- Four low-voltage differential data channels plus clock output
- 20-68 MHz PLL phase-lock input frequency range
- 7x clock multiplication from CLKIN synthesizer/PLL
- 3.0 to 3.6 V recommended supply range
- -40 to 85 °C characterized operating temperature
- Active-low shutdown disables LVDS drivers and clears registers
- Selectable data capture on rising or falling CLKIN edge
Typical Applications
- LVTTL parallel data serialization
- LVDS signal-chain links
- Clocked digital interface conversion
- 28-bit parallel bus reduction
- Differential data transmission
- Systems using 20-68 MHz input clocks
- Designs requiring active-low shutdown
Procurement Notes
When requesting a quote for SN65LVDS93, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What function does the SN65LVDS93 perform?
The SN65LVDS93 is an LVDS SerDes transmitter. It serializes 28 low-voltage TTL data channels plus clock into four low-voltage differential data channels plus clock, providing 28:4 channel compression.
What input clock range does the SN65LVDS93 support?
The PLL phase-lock input frequency range is 20-68 MHz. The device uses a clock synthesizer/PLL to multiply CLKIN by 7x, and maximum throughput is specified as 1.904 Gbit/s at the maximum input clock frequency.
What package is specified for this device?
The SN65LVDS93 is specified in a DGG 56-pin thin shrink small-outline package with 20 mil terminal pitch. Package power ratings are 1377 mW at TA <= 25°C, 882 mW at TA = 70°C, and 717 mW at TA = 85°C.
How does the shutdown input operate?
The shutdown function is active low. When SHTDN is asserted low, it inhibits the clock, shuts off the LVDS drivers, and clears the internal registers low. Disable time is specified as 250 ns maximum.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 25, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.