Specifications
| Type | Description |
|---|---|
| Part Number | SN65LVDT100 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | SOIC-8 4.90 mm x 3.91 mm; VSSOP-8 3.00 mm x 3.00 mm |
| Signaling Rate | >=2 Gbps; device feature / receiver input rates up to 2 Gbps |
| Output Logic Type | LVDS; SN65LVDT100 device option |
| Integrated Termination Resistor | Yes, 110 ohm differential line termination; SN65LVDT100 device option |
| VBB Reference Output | No; SN65LVDT100 device option |
| Operating Free-Air Temperature | -40 to 85 °C; recommended operating conditions |
| Supply Voltage | 3.0 V min, 3.3 V nom, 3.6 V max; recommended operating conditions |
| Differential Input Voltage Magnitude | 0.1 to 0.8 V; SN65LVDT100 or SN65LVDT101, recommended operating conditions |
| Input Voltage Range | 0 to 4 V; any combination of common-mode or input signals, recommended operating conditions |
| Supply Voltage Absolute Maximum | -0.5 to 4 V; over operating free-air temperature range |
| Input/Output Voltage Absolute Maximum | 0 to 4.3 V; A, B, Y, Z pins |
| Differential Input Voltage Absolute Maximum | 1 V; |VA - VB|, SN65LVDT100 and SN65LVDT101 only |
| HBM ESD Rating, Pins 2, 3, 5, 6, 7 | ±5000 V; ANSI/ESDA/JEDEC JS-001 |
| HBM ESD Rating, Other Pins | ±2000 V; all pins except 2, 3, 5, 6, 7; ANSI/ESDA/JEDEC JS-001 |
| CDM ESD Rating | ±1500 V; JEDEC JESD22-C101 |
| Junction-to-Ambient Thermal Resistance, D Package | 208 °C/W; D package, 8 pins |
| Junction-to-Ambient Thermal Resistance, DGK Package | 263 °C/W; DGK package, 8 pins |
| Power Dissipation Rating, D Package, TA <= 25°C | 151 mW |
| Power Dissipation Rating, DGK Package, TA <= 25°C | 377 mW |
| Power Dissipation Rating, D Package, TA <= 85°C | 192 mW |
| Power Dissipation Rating, DGK Package, TA <= 85°C | 481 mW |
| Supply Current | 25 mA typ, 30 mA max; SN65LVDT100, no load or input |
| Device Power Dissipation | 110 mW typ; SN65LVDT100, RL=100 ohm, no input |
| Positive-Going Differential Input Voltage Threshold | 100 mV max; SN65LVDT100 input characteristics, see Figure 30 and Table 1 |
| Negative-Going Differential Input Voltage Threshold | -100 mV min; SN65LVDT100 input characteristics, see Figure 30 and Table 1 |
| Input Current, VI=0 V or 2.4 V | -40 to 40 µA; other input open |
| Input Current, VI=4 V | 66 µA max; other input open |
| Power-Off Input Current, VI=0 V or 2.4 V | -40 to 40 µA; VCC=1.5 V, other input open |
| Power-Off Input Current, VI=4 V | 66 µA max; VCC=1.5 V, other input open |
| Differential Input Resistance | 90 ohm min, 110 ohm typ, 132 ohm max; VID=300 mV or 500 mV, VIC=0 V or 2.4 V |
| Differential Input Resistance, VCC=0 V | 90 ohm min, 110 ohm typ, 132 ohm max; VID=300 mV or 500 mV, VIC=0 V or 2.4 V |
| Small-Signal Differential Input Capacitance | 0.6 pF typ; VI=1.2 V |
| LVDS Differential Output Voltage Magnitude | 247 mV min, 340 mV typ, 454 mV max; SN65LVDT100 output characteristics, see Figure 31 |
| Change in Differential Output Voltage Magnitude Between Logic States | -50 to 50 mV; SN65LVDT100 output characteristics, see Figure 31 |
| Steady-State Common-Mode Output Voltage | 1.125 to 1.375 V; SN65LVDT100 output characteristics |
| Change in Steady-State Common-Mode Output Voltage Between Logic States | -50 to 50 mV; SN65LVDT100 output characteristics, see Figure 32 |
| Peak-to-Peak Common-Mode Output Voltage | 50 mV typ, 150 mV max; SN65LVDT100 output characteristics |
| Short-Circuit Output Current | -24 to 24 mA; VO(Y) or VO(Z)=0 V |
| Differential Short-Circuit Output Current | -12 to 12 mA; VOD=0 V |
| Propagation Delay Low-to-High | 300 ps min, 470 ps typ, 800 ps max; SN65LVDT100, see Figure 33 |
| Propagation Delay High-to-Low | 300 ps min, 470 ps typ, 800 ps max; SN65LVDT100, see Figure 33 |
| Differential Output Signal Rise Time | 220 ps typ; 20% to 80% |
| Differential Output Signal Fall Time | 220 ps typ; 20% to 80% |
| Pulse Skew | 5 ps typ, 50 ps max; |tPHL - tPLH| |
| Part-to-Part Skew | 100 ps max; VID=0.2 V, see Figure 33 |
| RMS Period Jitter | 1 ps typ, 3.7 ps max; 1 GHz 50% duty-cycle square-wave input; VID=200 mV, VIC=1.2 V |
| Peak Cycle-to-Cycle Jitter | 6 ps typ, 23 ps max; VID=200 mV, VIC=1.2 V, see Figure 34 |
| Peak-to-Peak Jitter | 28 ps typ, 65 ps max; 2 GHz PRBS, 2^23-1 run length; VID=200 mV, VIC=1.2 V, see Figure 34 |
| Peak-to-Peak Deterministic Jitter | 17 ps typ, 48 ps max; 2 GHz PRBS, 2^7-1 run length; VID=200 mV, VIC=1.2 V, see Figure 34 |
| Datasheet Status | request_only |
Product Overview
Recommended operating conditions include a 3.0 V minimum, 3.3 V nominal, and 3.6 V maximum supply voltage over -40 to 85 °C free-air temperature. The SN65LVDT100 accepts 0.1 V to 0.8 V differential input voltage magnitude and supports 0 V to 4 V input voltage range for any combination of common-mode or input signals.
Electrical data includes 25 mA typical and 30 mA maximum supply current with no load or input, 110 mW typical device power dissipation with RL = 100 ohm and no input, 247 mV to 454 mV LVDS differential output voltage magnitude, and 1.125 V to 1.375 V steady-state common-mode output voltage. Timing parameters include 470 ps typical propagation delay, 220 ps typical rise and fall times, 5 ps typical pulse skew, and jitter specifications for 1 GHz square-wave and 2 GHz PRBS input conditions.
Package options are SOIC-8 4.90 mm x 3.91 mm and VSSOP-8 3.00 mm x 3.00 mm. Thermal and power ratings are package-specific, with junction-to-ambient thermal resistance of 208 °C/W for the D package and 263 °C/W for the DGK package.
Key Features
- Receiver input rates up to 2 Gbps
- LVDS output logic for SN65LVDT100 option
- Integrated 110 ohm differential line termination
- No VBB reference output on this option
- 3.0 V to 3.6 V recommended supply range
- -40 to 85 °C free-air operating range
- 0.1 V to 0.8 V differential input magnitude
- 247 mV to 454 mV LVDS differential output
- 470 ps typical propagation delay
- 220 ps typical differential rise and fall times
- 5 ps typical pulse skew
- 1 ps typical RMS period jitter
Typical Applications
- High-speed differential translation
- LVDS signal repeating
- Terminated differential input links
- 2 Gbps receiver input paths
- Jitter-sensitive signal-chain interfaces
- 3.3 V differential logic systems
- SOIC-8 or VSSOP-8 assemblies
Procurement Notes
When requesting a quote for SN65LVDT100, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What output logic type does the SN65LVDT100 provide?
The SN65LVDT100 device option provides LVDS output logic. Its LVDS differential output voltage magnitude is specified from 247 mV minimum to 454 mV maximum, with 340 mV typical under the stated output characteristics.
Does the SN65LVDT100 include input line termination?
Yes. The SN65LVDT100 device option includes an integrated 110 ohm differential line termination resistor. Differential input resistance is specified as 90 ohm minimum, 110 ohm typical, and 132 ohm maximum under the listed VID and VIC conditions.
What supply and temperature range are recommended?
Recommended operating conditions specify a 3.0 V minimum, 3.3 V nominal, and 3.6 V maximum supply voltage. The operating free-air temperature range is -40 to 85 °C.
What timing parameters are specified for this repeater?
Propagation delay is specified at 300 ps minimum, 470 ps typical, and 800 ps maximum for both low-to-high and high-to-low paths. Differential output rise and fall times are each 220 ps typical.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.