Specifications
| Type | Description |
|---|---|
| Part Number | SN74AHC125 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package Case | D (SOIC-14) 8.65 mm x 3.91 mm; DB (SSOP-14) 6.20 mm x 5.30 mm; DGV (TVSOP-14) 3.60 mm x 4.40 mm; PW (TSSOP-14) 5.00 mm x 4.40 mm; N (PDIP-14) 19.30 mm x 6.35 mm; NS (SO-14) 10.30 mm x 5.30 mm; RGY (VQFN-14) 3.50 mm x 3.50 mm; BQA (WQFN-14) 3.00 mm x 2.50 mm |
| Supply voltage operating range | 2 to 5.5 V; recommended operating conditions; source page 5 |
| Logic channels | 4 independent buffer gates; quadruple bus buffer gates with 3-state outputs; source page 1 |
| Output enable polarity | Output disabled when OE is high; output follows A when OE is low; per gate output-enable input; source page 1 |
| Latch-up performance | >250 mA; per JESD 17; source page 1 |
| Supply voltage absolute maximum | -0.5 to 7 V; over operating free-air temperature range; source page 5 |
| Input voltage absolute maximum | -0.5 to 7 V; input/output current ratings observed where applicable; source page 5 |
| Output voltage absolute maximum | -0.5 to VCC + 0.5 V; input/output current ratings observed where applicable; source page 5 |
| Input clamp current | -20 mA; VI < 0 V; source page 5 |
| Output clamp current | +/-20 mA; VO < 0 V or VO > VCC; source page 5 |
| Continuous output current | +/-25 mA; VO = 0 V to VCC; source page 5 |
| Continuous current through VCC or GND | +/-50 mA; absolute maximum rating; source page 5 |
| Virtual operating junction temperature | 150 °C max; absolute maximum rating, TJ; source page 5 |
| Storage temperature | -65 to 150 °C; absolute maximum rating, Tstg; source page 5 |
| ESD rating HBM | +/-1500 V; ANSI/ESDA/JEDEC JS-001; source page 5 |
| ESD rating CDM | +/-1000 V; JEDEC JESD22-C101; source page 5 |
| High-level input voltage VIH | 1.5 V min; VCC = 2 V; source page 5 |
| High-level input voltage VIH | 2.1 V min; VCC = 3 V; source page 5 |
| High-level input voltage VIH | 3.85 V min; VCC = 5.5 V; source page 5 |
| Low-level input voltage VIL | 0.5 V max; VCC = 2 V; source page 5 |
| Low-level input voltage VIL | 0.9 V max; VCC = 3 V; source page 5 |
| Low-level input voltage VIL | 1.65 V max; VCC = 5.5 V; source page 5 |
| Input voltage recommended range | 0 to 5.5 V; recommended operating conditions; source page 5 |
| Output voltage recommended range | 0 to VCC V; recommended operating conditions; source page 5 |
| High-level output current IOH | -50 µA; VCC = 2 V; source page 5 |
| High-level output current IOH | -4 mA; VCC = 3.3 V +/-0.3 V; source page 5 |
| High-level output current IOH | -8 mA; VCC = 5 V +/-0.5 V; source page 5 |
| Low-level output current IOL | 50 µA; VCC = 2 V; source page 5 |
| Low-level output current IOL | 4 mA; VCC = 3.3 V +/-0.3 V; source page 5 |
| Low-level output current IOL | 8 mA; VCC = 5 V +/-0.5 V; source page 5 |
| Input transition rise or fall rate | 100 ns/V max; VCC = 3.3 V +/-0.3 V; source page 5 |
| Input transition rise or fall rate | 20 ns/V max; VCC = 5 V +/-0.5 V; source page 5 |
| Operating free-air temperature | -40 to 125 °C; recommended SN74AHC125 operating range; source page 5 |
| High-level output voltage VOH | 1.9 V min, 2 V typ; IOH = -50 µA, VCC = 2 V, TA = 25°C; source page 6 |
| High-level output voltage VOH | 2.9 V min, 3 V typ; IOH = -50 µA, VCC = 3 V, TA = 25°C; source page 6 |
| High-level output voltage VOH | 4.4 V min, 4.5 V typ; IOH = -50 µA, VCC = 4.5 V, TA = 25°C; source page 6 |
| High-level output voltage VOH | 2.48 V min; IOH = -4 mA, VCC = 3 V, SN74AHC125 TA = -40°C to 125°C; source page 6 |
| High-level output voltage VOH | 3.8 V min; IOH = -8 mA, VCC = 4.5 V, SN74AHC125 TA = -40°C to 125°C; source page 6 |
| Low-level output voltage VOL | 0.1 V max; IOL = 50 µA, VCC = 2 V, SN74AHC125 TA = -40°C to 125°C; source page 7 |
| Low-level output voltage VOL | 0.1 V max; IOL = 50 µA, VCC = 3 V, SN74AHC125 TA = -40°C to 125°C; source page 7 |
| Low-level output voltage VOL | 0.1 V max; IOL = 50 µA, VCC = 4.5 V, SN74AHC125 TA = -40°C to 125°C; source page 7 |
| Low-level output voltage VOL | 0.5 V max; IOL = 4 mA, VCC = 3 V, SN74AHC125 TA = -40°C to 125°C; source page 7 |
| Low-level output voltage VOL | 0.5 V max; IOL = 8 mA, VCC = 4.5 V, SN74AHC125 TA = -40°C to 125°C; source page 7 |
| Input leakage current II | +/-1 µA max; VI = 5.5 V or GND, VCC = 0 V to 5.5 V, SN74AHC125 TA = -40°C to 125°C; source page 7 |
| Off-state output current IOZ | +/-2.5 µA max; VO = VCC or GND, VCC = 5.5 V, SN74AHC125 TA = -40°C to 125°C; source page 7 |
| Supply current ICC | 40 µA max; VI = VCC or GND, IO = 0, VCC = 5.5 V, SN74AHC125 TA = -40°C to 125°C; source page 7 |
| Input capacitance Ci | 4 pF typ, 10 pF max; VI = VCC or GND, VCC = 5 V, TA = 25°C; source page 7 |
| Propagation delay tPHL/tPLH | 1 to 9.5 ns; A to Y, CL = 15 pF, VCC = 3.3 V +/-0.3 V, SN74AHC125 TA = -40°C to 125°C; source page 8 |
| Output enable delay tPZL/tPZH | 9.5 ns max; OE to Y, CL = 15 pF, VCC = 3.3 V +/-0.3 V, SN74AHC125 TA = -40°C to 125°C; source page 8 |
| Output disable delay tPLZ/tPHZ | 1 to 11.5 ns; OE to Y, CL = 15 pF, VCC = 3.3 V +/-0.3 V, SN74AHC125 TA = -40°C to 125°C; source page 8 |
| Propagation delay tPHL/tPLH | 1 to 13 ns; A to Y, CL = 50 pF, VCC = 3.3 V +/-0.3 V, SN74AHC125 TA = -40°C to 125°C; source page 8 |
| Output enable delay tPZL/tPZH | 1 to 13 ns; OE to Y, CL = 50 pF, VCC = 3.3 V +/-0.3 V, SN74AHC125 TA = -40°C to 125°C; source page 8 |
| Output disable delay tPLZ/tPHZ | 1 to 15 ns; OE to Y, CL = 50 pF, VCC = 3.3 V +/-0.3 V, SN74AHC125 TA = -40°C to 125°C; source page 8 |
| Output skew tsk(o) | 1.5 ns max; OE to Y, CL = 50 pF, VCC = 3.3 V +/-0.3 V, SN74AHC125 TA = -40°C to 85°C; source page 8 |
| Propagation delay tPLH/tPHL | 1 to 6.5 ns; A to Y, CL = 15 pF, VCC = 5 V +/-0.5 V, SN74AHC125 TA = -40°C to 125°C; source page 9 |
| Output enable delay tPZH/tPZL | 1 to 6 ns; OE to Y, CL = 15 pF, VCC = 5 V +/-0.5 V, SN74AHC125 TA = -40°C to 125°C; source page 9 |
| Output disable delay tPHZ/tPLZ | 1 to 8 ns; OE to Y, CL = 15 pF, VCC = 5 V +/-0.5 V, SN74AHC125 TA = -40°C to 125°C; source page 9 |
| Propagation delay tPLH/tPHL | 1 to 8.5 ns; A to Y, CL = 50 pF, VCC = 5 V +/-0.5 V, SN74AHC125 TA = -40°C to 125°C; source page 9 |
| Thermal resistance RthetaJA | 124.5 °C/W; D SOIC-14 package; source page 6 |
| Thermal resistance RthetaJA | 107.3 °C/W; DB SSOP-14 package; source page 6 |
| Thermal resistance RthetaJA | 89.9 °C/W; DGV TVSOP-14 package; source page 6 |
| Thermal resistance RthetaJA | 134.6 °C/W; PW TSSOP-14 package; source page 6 |
| Thermal resistance RthetaJA | 147.7 °C/W; NS SO-14 package; source page 6 |
| Thermal resistance RthetaJA | 56.3 °C/W; RGY VQFN-14 package; source page 6 |
| Thermal resistance RthetaJA | 87.1 °C/W; BQA WQFN-14 package; source page 6 |
| Thermal resistance RthetaJA | 88.3 °C/W; N PDIP-14 package; source page 6 |
| Datasheet Status | request_only |
Product Overview
The SN74AHC125 is a Texas Instruments quad bus buffer gate in the Signal_Chain category. It provides four independent buffer gates with 3-state outputs. Each gate has its own output-enable input: the output is disabled when OE is high, and the output follows A when OE is low.
Recommended operation covers a 2 to 5.5 V supply range, 0 to 5.5 V input voltage range, and 0 to VCC output voltage range. The device is specified for -40 to 125 °C free-air operation. Drive-current conditions include IOH/IOL ratings at 2 V, 3.3 V ±0.3 V, and 5 V ±0.5 V supplies.
Package coverage includes SOIC-14, SSOP-14, TVSOP-14, TSSOP-14, PDIP-14, SO-14, VQFN-14, and WQFN-14 options, with RθJA values ranging from 56.3 °C/W for RGY VQFN-14 to 147.7 °C/W for NS SO-14. These package and thermal options support board-level selection where footprint and thermal resistance are design constraints.
Key Features
- Four independent buffer gates with 3-state outputs
- Per-gate OE control disables output when high
- Output follows A input when OE is low
- Recommended supply operating range is 2 to 5.5 V
- Recommended operating temperature is -40 to 125 °C
- Input voltage range is 0 to 5.5 V
- Off-state output current is +/-2.5 µA maximum
- Supply current is 40 µA maximum at 5.5 V
- Latch-up performance exceeds 250 mA per JESD 17
- Multiple 14-pin package options are specified
Typical Applications
- 3-state bus buffering
- Logic signal isolation
- Buffered signal routing
- Shared bus output control
- Low-voltage digital interfaces
- Package-constrained logic boards
Procurement Notes
When requesting a quote for SN74AHC125, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the SN74AHC125?
The SN74AHC125 is a Texas Instruments quad bus buffer gate. It contains four independent buffer gates with 3-state outputs, and each gate has its own output-enable input.
What supply voltage range does SN74AHC125 support?
Under recommended operating conditions, SN74AHC125 supports a 2 to 5.5 V supply voltage range. The absolute maximum supply voltage rating is -0.5 to 7 V.
How does the output enable input control each output?
For each gate, the output is disabled when OE is high. When OE is low, the output follows the A input, giving per-channel control of the 3-state output.
Which package options are listed for SN74AHC125?
Listed package options include D SOIC-14, DB SSOP-14, DGV TVSOP-14, PW TSSOP-14, N PDIP-14, NS SO-14, RGY VQFN-14, and BQA WQFN-14.
What timing values are specified at 5 V operation?
At VCC = 5 V +/-0.5 V and CL = 15 pF, the propagation delay is 1 to 6.5 ns, output enable delay is 1 to 6 ns, and output disable delay is 1 to 8 ns.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 13, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.