SN74AHC86 Quad 2-Input XOR Gates

Texas Instruments Signal_Chain — specifications, applications, sourcing support and RFQ.

SN74AHC86 Quad 2-Input XOR Gates

RFQ Available Sourcing Support Alternative Matching RoHS
Part Number
SN74AHC86
Manufacturer
Texas Instruments
Package
BQA (WQFN-14), D (SOIC-14), DB (SSOP-14), DGV (TVSOP-14), N (PDIP-14), NS (SOP-14), PW (TSSOP-14), RGY (VQFN-14), J (CDIP-14), W (CFP-14), FK (LCCC-20)
Category
Signal Chain
Product Type
Operational Amplifier

Quick Sourcing Note

SN74AHC86 from Texas Instruments is a Signal_Chain quad 2-input XOR gate device implementing Y = A XOR B in positive logic for each gate. It supports a recommended 2 to 5.5 V supply range, 0 to 5.5 V input voltage, and 0 to VCC output voltage. The SN74AHC86 operating free-air temperature range is -40 to 125 °C. Package options include WQFN-14, SOIC-14, SSOP-14, TVSOP-14, PDIP-14, SOP-14, TSSOP-14, VQFN-14, CDIP-14, CFP-14, and LCCC-20. Timing data includes propagation delays down to typical 4.8 ns at 5 V ± 0.5 V with 15 pF load.

Specifications

TypeDescription
Part NumberSN74AHC86
ManufacturerTexas Instruments
Product TypeOperational Amplifier
CategorySignal Chain
Package / CaseBQA (WQFN-14), D (SOIC-14), DB (SSOP-14), DGV (TVSOP-14), N (PDIP-14), NS (SOP-14), PW (TSSOP-14), RGY (VQFN-14), J (CDIP-14), W (CFP-14), FK (LCCC-20)
Logic FunctionY = A XOR B; positive logic, each gate
Number of Gates4; quadruple 2-input exclusive-OR gates
Inputs per Gate2; each exclusive-OR gate
Recommended Supply Voltage2 to 5.5 V; SN54AHC86 and SN74AHC86
Absolute Maximum Supply Voltage-0.5 to 7 V; over operating free-air temperature range
Absolute Maximum Input Voltage-0.5 to 7 V; input and output voltage ratings may be exceeded if current ratings are observed
Absolute Maximum Output Voltage-0.5 to VCC + 0.5 V; input and output voltage ratings may be exceeded if current ratings are observed
Input Clamp Current-20 mA; VI < 0
Output Clamp Current±20 mA; VO < 0 or VO > VCC
Continuous Output Current±25 mA; VO = 0 to VCC
Continuous Current Through VCC or GND±50 mA; absolute maximum rating
Storage Temperature Range-65 to 150 °C; absolute maximum rating
High-Level Input Voltage at VCC = 2 Vmin 1.5 V
High-Level Input Voltage at VCC = 3 Vmin 2.1 V
High-Level Input Voltage at VCC = 5.5 Vmin 3.85 V
Low-Level Input Voltage at VCC = 2 Vmax 0.5 V
Low-Level Input Voltage at VCC = 3 Vmax 0.9 V
Low-Level Input Voltage at VCC = 5.5 Vmax 1.65 V
Recommended Input Voltage0 to 5.5 V; SN54AHC86 and SN74AHC86
Recommended Output Voltage0 to VCC; SN54AHC86 and SN74AHC86
High-Level Output Current at VCC = 2 Vmax -50 µA
High-Level Output Current at VCC = 3.3 V ± 0.3 Vmax -4 mA
High-Level Output Current at VCC = 5 V ± 0.5 Vmax -8 mA
Low-Level Output Current at VCC = 2 Vmax 50 µA
Low-Level Output Current at VCC = 3.3 V ± 0.3 Vmax 4 mA
Low-Level Output Current at VCC = 5 V ± 0.5 Vmax 8 mA
Input Transition Rise or Fall Rate at 3.3 Vmax 100 ns/V; VCC = 3.3 V ± 0.3 V
Input Transition Rise or Fall Rate at 5 Vmax 20 ns/V; VCC = 5 V ± 0.5 V
Operating Free-Air Temperature for SN54AHC86-55 to 125 °C
Operating Free-Air Temperature for SN74AHC86-40 to 125 °C
Junction-to-Ambient Thermal Resistance, D SOIC-14124.5 °C/W
Junction-to-Ambient Thermal Resistance, DB SSOP-1496 °C/W
Junction-to-Ambient Thermal Resistance, DGV TVSOP-14127 °C/W
Junction-to-Ambient Thermal Resistance, N PDIP-1480 °C/W
Junction-to-Ambient Thermal Resistance, NS SOP-1476 °C/W
Junction-to-Ambient Thermal Resistance, PW TSSOP-14147.7 °C/W
Junction-to-Ambient Thermal Resistance, RGY VQFN-1447 °C/W
Junction-to-Ambient Thermal Resistance, BQA WQFN-1488.3 °C/W
High-Level Output Voltage, IOH = -50 µA, VCC = 2 Vmin 1.9 V, typ 2 V; TA = 25°C
High-Level Output Voltage, IOH = -50 µA, VCC = 3 Vmin 2.9 V, typ 3 V; TA = 25°C
High-Level Output Voltage, IOH = -50 µA, VCC = 4.5 Vmin 4.4 V, typ 4.5 V; TA = 25°C
High-Level Output Voltage, IOH = -4 mA, VCC = 3 Vmin 2.58 V; TA = 25°C
High-Level Output Voltage, IOH = -8 mA, VCC = 4.5 Vmin 3.94 V; TA = 25°C
Low-Level Output Voltage, IOL = 50 µA, VCC = 2 Vtyp 0.1 V, max 0.1 V
Low-Level Output Voltage, IOL = 50 µA, VCC = 3 Vtyp 0.1 V, max 0.1 V
Low-Level Output Voltage, IOL = 50 µA, VCC = 4.5 Vtyp 0.1 V, max 0.1 V
Low-Level Output Voltage, IOL = 4 mA, VCC = 3 Vtyp 0.36 V, max 0.5 V; TA = 25°C
Low-Level Output Voltage, IOL = 8 mA, VCC = 4.5 Vtyp 0.36 V, max 0.5 V; TA = 25°C
Input Currentmax ±0.1 µA at TA = 25°C; max ±1 µA over temperature; VI = 5.5 V or GND, VCC = 0 V to 5.5 V
Supply Currenttyp 2 µA, max 20 µA; VI = VCC or GND, IO = 0, VCC = 5.5 V
Input Capacitancetyp 4 pF, max 10 pF; VI = VCC or GND, VCC = 5 V
Propagation Delay Low-to-High, 3.3 V, 15 pFtyp 7 ns, max 11 ns at TA = 25°C; min 1 ns, max 13 ns over recommended range; A or B to Y
Propagation Delay High-to-Low, 3.3 V, 15 pFtyp 7 ns, max 11 ns at TA = 25°C; min 1 ns, max 13 ns over recommended range; A or B to Y
Propagation Delay Low-to-High, 3.3 V, 50 pFtyp 9.5 ns, max 14.5 ns at TA = 25°C; min 1 ns, max 16.5 ns over recommended range; A or B to Y
Propagation Delay High-to-Low, 3.3 V, 50 pFtyp 9.5 ns, max 14.5 ns at TA = 25°C; min 1 ns, max 16.5 ns over recommended range; A or B to Y
Propagation Delay Low-to-High, 5 V, 15 pFtyp 4.8 ns, max 6.8 ns at TA = 25°C; min 1 ns, max 8 ns over recommended range; A or B to Y
Propagation Delay High-to-Low, 5 V, 15 pFtyp 4.8 ns, max 6.8 ns at TA = 25°C; min 1 ns, max 8 ns over recommended range; A or B to Y
Propagation Delay Low-to-High, 5 V, 50 pFtyp 6.3 ns, max 8.8 ns at TA = 25°C; min 1 ns, max 10 ns over recommended range; A or B to Y
Propagation Delay High-to-Low, 5 V, 50 pFtyp 6.3 ns, max 8.8 ns at TA = 25°C; min 1 ns, max 10 ns over recommended range; A or B to Y
Quiet Output Maximum Dynamic VOLtyp 0.3 V, max 0.8 V; VCC = 5 V, CL = 50 pF, TA = 25°C, surface-mount packages only
Quiet Output Minimum Dynamic VOLtyp -0.3 V, min -0.8 V; VCC = 5 V, CL = 50 pF, TA = 25°C, surface-mount packages only
Quiet Output Minimum Dynamic VOHmin 4.4 V; VCC = 5 V, CL = 50 pF, TA = 25°C, surface-mount packages only
High-Level Dynamic Input Voltagetyp 3.5 V; VCC = 5 V, CL = 50 pF, TA = 25°C, surface-mount packages only
Low-Level Dynamic Input Voltagetyp 1.5 V; VCC = 5 V, CL = 50 pF, TA = 25°C, surface-mount packages only
Power Dissipation Capacitancetyp 18 pF; no load, f = 1 MHz, VCC = 5 V, TA = 25°C
Latch-Up Performanceexceeds 250 mA; per JESD 17
ESD Human-Body Modelexceeds 2000 V; JESD 22, A114-A
ESD Machine Modelexceeds 200 V; JESD 22, A115-A
ESD Charged-Device Modelexceeds 1000 V; JESD 22, C101
Datasheet Statusrequest_only

Product Overview

The SN74AHC86 is a Texas Instruments quad 2-input exclusive-OR gate device. In positive logic, each gate implements Y = A XOR B, providing four independent XOR functions with two inputs per gate. The device is categorized as Signal_Chain content here and is specified for logic-level signal processing functions that require exclusive-OR behavior.

Recommended operating conditions cover a 2 to 5.5 V supply range, 0 to 5.5 V input voltage, and 0 to VCC output voltage. The SN74AHC86 version is specified for -40 to 125 °C operating free-air temperature, while the related SN54AHC86 range is -55 to 125 °C. Input thresholds are specified at 2 V, 3 V, and 5.5 V VCC levels.

Package options include BQA WQFN-14, D SOIC-14, DB SSOP-14, DGV TVSOP-14, N PDIP-14, NS SOP-14, PW TSSOP-14, RGY VQFN-14, J CDIP-14, W CFP-14, and FK LCCC-20. Thermal resistance varies by package, from 47 °C/W for RGY VQFN-14 to 147.7 °C/W for PW TSSOP-14.

Key Features

  • Four independent 2-input exclusive-OR logic gates
  • Positive-logic function implements Y = A XOR B
  • Recommended supply voltage range is 2 to 5.5 V
  • SN74AHC86 operating free-air range is -40 to 125 °C
  • Input voltage recommendation covers 0 to 5.5 V
  • Output voltage recommendation covers 0 to VCC
  • Typical supply current is 2 µA at 5.5 V
  • Typical input capacitance is 4 pF at 5 V
  • Typical 5 V propagation delay is 4.8 ns at 15 pF
  • Latch-up performance exceeds 250 mA per JESD 17

Typical Applications

  • Exclusive-OR logic stages
  • Parity generation circuits
  • Parity checking circuits
  • Digital signal comparison
  • Logic-level signal conditioning
  • Control logic gating
  • Multi-gate XOR implementations

Procurement Notes

When requesting a quote for SN74AHC86, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.

If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.

For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.

FAQ

What logic function does the SN74AHC86 implement?

The SN74AHC86 implements four positive-logic exclusive-OR gates. For each gate, the datasheet function is Y = A XOR B, with two logic inputs feeding each output.

What supply voltage range is recommended for SN74AHC86 operation?

The recommended supply voltage range for the SN74AHC86 is 2 to 5.5 V. The recommended input voltage range is 0 to 5.5 V, and the recommended output voltage range is 0 to VCC.

What packages are listed for the SN74AHC86?

The package list includes WQFN-14, SOIC-14, SSOP-14, TVSOP-14, PDIP-14, SOP-14, TSSOP-14, VQFN-14, CDIP-14, CFP-14, and LCCC-20 package options.

What propagation delay is specified at 5 V operation?

At VCC = 5 V ± 0.5 V and CL = 15 pF, both low-to-high and high-to-low propagation delays from A or B to Y are specified as typical 4.8 ns and maximum 6.8 ns at TA = 25°C.

Technical Review & Sourcing Note

Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.

This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.

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