Specifications
| Type | Description |
|---|---|
| Part Number | SN74HC125 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Component Type | Other |
| Package Case | SOIC-14 8.70 mm x 3.90 mm; SSOP-14 6.50 mm x 5.30 mm; PDIP-14 19.30 mm x 6.40 mm; SO-14 10.20 mm x 5.30 mm; TSSOP-14 5.00 mm x 4.40 mm; CDIP-14 21.30 mm x 7.60 mm; LCCC-20 8.90 mm x 8.90 mm |
| Logic Function | Y = A; positive logic buffer function |
| Number of Channels | 4 independent buffers; 3-state outputs |
| Output Enable Polarity | Active low; OE input controls each channel output enable |
| Recommended Supply Voltage | 2 V min, 5 V nom, 6 V max; over operating free-air temperature range |
| Operating Free-Air Temperature | -55°C to 125°C; recommended operating conditions |
| High-Level Input Voltage at VCC = 2 V | 1.5 V min |
| High-Level Input Voltage at VCC = 4.5 V | 3.15 V min |
| High-Level Input Voltage at VCC = 6 V | 4.2 V min |
| Low-Level Input Voltage at VCC = 2 V | 0.5 V max |
| Low-Level Input Voltage at VCC = 4.5 V | 1.35 V max |
| Low-Level Input Voltage at VCC = 6 V | 1.8 V max |
| Input Voltage Range | 0 V to VCC; recommended operating conditions |
| Output Voltage Range | 0 V to VCC; recommended operating conditions |
| Input Transition Time at VCC = 2 V | 1000 ns max |
| Input Transition Time at VCC = 4.5 V | 500 ns max |
| Input Transition Time at VCC = 6 V | 400 ns max |
| Absolute Maximum Supply Voltage | -0.5 V to 7 V; over operating free-air temperature range |
| Input Clamp Current | +/-20 mA max; VI < 0 or VI > VCC |
| Output Clamp Current | +/-20 mA max; VO < 0 or VO > VCC |
| Continuous Output Current | +/-35 mA max; VO = 0 to VCC |
| Continuous Current Through VCC or GND | +/-70 mA max; absolute maximum rating |
| Junction Temperature | 150°C max; absolute maximum rating, guaranteed by design |
| Storage Temperature | -65°C to 150°C; absolute maximum rating |
| ESD Rating HBM | +/-2000 V; per ANSI/ESDA/JEDEC JS-001 |
| ESD Rating CDM | +/-500 V; per JEDEC JESD22-C101 |
| High-Level Output Voltage, IOH = -20 uA, VCC = 2 V | 1.9 V min, 1.998 V typ; VI = VIH or VIL, TA = 25°C |
| High-Level Output Voltage, IOH = -20 uA, VCC = 4.5 V | 4.4 V min, 4.499 V typ; VI = VIH or VIL, TA = 25°C |
| High-Level Output Voltage, IOH = -20 uA, VCC = 6 V | 5.9 V min, 5.999 V typ; VI = VIH or VIL, TA = 25°C |
| High-Level Output Voltage, IOH = -6 mA, VCC = 4.5 V | 3.98 V min, 4.3 V typ; VI = VIH or VIL, TA = 25°C |
| High-Level Output Voltage, IOH = -7.8 mA, VCC = 6 V | 5.48 V min, 5.8 V typ; VI = VIH or VIL, TA = 25°C |
| Low-Level Output Voltage, IOL = 20 uA, VCC = 2 V | 0.002 V typ, 0.1 V max; VI = VIH or VIL, TA = 25°C |
| Low-Level Output Voltage, IOL = 20 uA, VCC = 4.5 V | 0.001 V typ, 0.1 V max; VI = VIH or VIL, TA = 25°C |
| Low-Level Output Voltage, IOL = 20 uA, VCC = 6 V | 0.001 V typ, 0.1 V max; VI = VIH or VIL, TA = 25°C |
| Low-Level Output Voltage, IOL = 6 mA, VCC = 4.5 V | 0.17 V typ, 0.26 V max; VI = VIH or VIL, TA = 25°C |
| Low-Level Output Voltage, IOL = 7.8 mA, VCC = 6 V | 0.15 V typ, 0.26 V max; VI = VIH or VIL, TA = 25°C |
| Input Leakage Current | +/-0.1 uA max at 25°C; +/-1 uA max over -40°C to 85°C; VI = VCC or 0, VCC = 6 V |
| Three-State Leakage Current | +/-0.01 uA typ, +/-0.5 uA max at 25°C; +/-5 uA max over -40°C to 85°C; VO = VCC or 0, VCC = 6 V |
| Supply Current | 8 uA max at 25°C; 80 uA max over -40°C to 85°C; VI = VCC or 0, IO = 0, VCC = 6 V |
| Input Capacitance | 3 pF typ, 10 pF max; VCC = 2 V to 6 V |
| Propagation Delay, A to Y, VCC = 2 V | 47 ns typ, 120 ns max at 25°C; 180 ns max over -40°C to 85°C; CL = 50 pF |
| Propagation Delay, A to Y, VCC = 4.5 V | 14 ns typ, 24 ns max at 25°C; 36 ns max over -40°C to 85°C; CL = 50 pF |
| Propagation Delay, A to Y, VCC = 6 V | 11 ns typ, 20 ns max at 25°C; 31 ns max over -40°C to 85°C; CL = 50 pF |
| Enable Delay, OE to Y, VCC = 4.5 V | 16 ns typ, 24 ns max at 25°C; 36 ns max over -40°C to 85°C; CL = 50 pF |
| Disable Delay, OE to Y, VCC = 4.5 V | 17 ns typ, 24 ns max at 25°C; 36 ns max over -40°C to 85°C; CL = 50 pF |
| Output Transition Time | 8 ns typ, 12 ns max at 25°C; 18 ns max over -40°C to 85°C; Y output, CL = 50 pF, VCC = 4.5 V |
| Power Dissipation Capacitance | 45 pF typ per gate; no load, VCC = 2 V to 6 V, TA = 25°C |
| Junction-to-Ambient Thermal Resistance, SN74HC125D | 133.6°C/W; SOIC-14 package |
| Junction-to-Ambient Thermal Resistance, SN74HC125DB | 108.0°C/W; SSOP-14 package |
| Junction-to-Ambient Thermal Resistance, SN74HC125N | 63.0°C/W; PDIP-14 package |
| Junction-to-Ambient Thermal Resistance, SN74HC125NS | 122.6°C/W; SO-14 package |
| Junction-to-Ambient Thermal Resistance, SN74HC125PW | 151.7°C/W; TSSOP-14 package |
| Datasheet Status | request_only |
Product Overview
The SN74HC125 is a Texas Instruments quad 3-state buffer in the Signal_Chain category. It implements a positive-logic buffer function, Y = A, across four independent buffers. Each channel output is controlled by an active-low OE input, allowing the output to drive the buffered input value or enter the high-impedance 3-state condition.
Recommended supply operation is 2 V minimum, 5 V nominal, and 6 V maximum over the operating free-air temperature range of -55°C to 125°C. Input and output voltage ranges are both specified from 0 V to VCC. At VCC = 4.5 V, the device specifies VIH of 3.15 V minimum, VIL of 1.35 V maximum, and 500 ns maximum input transition time.
The device is available in multiple package formats, including SOIC-14, SSOP-14, PDIP-14, SO-14, TSSOP-14, CDIP-14, and LCCC-20. Timing characteristics include 14 ns typical A-to-Y propagation delay at VCC = 4.5 V and CL = 50 pF, with OE-to-Y enable and disable delays of 16 ns and 17 ns typical under the same supply and load conditions.
Key Features
- Four independent buffers with 3-state outputs
- Positive-logic buffer function with Y equals A
- Active-low OE input controls each channel output
- Recommended supply range from 2 V to 6 V
- Input and output voltage ranges span 0 V to VCC
- -55°C to 125°C operating free-air temperature range
- 14 ns typical A-to-Y delay at 4.5 V
- 16 ns typical OE-to-Y enable delay at 4.5 V
- 3 pF typical input capacitance
- HBM ESD rating of +/-2000 V
Typical Applications
- Digital bus isolation
- Shared logic signal lines
- Controlled output enable buffering
- CMOS logic signal buffering
- 3-state output interfaces
- Multi-channel digital routing
Procurement Notes
When requesting a quote for SN74HC125, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What logic function does the SN74HC125 implement?
The SN74HC125 implements a positive-logic buffer function where Y = A. It contains four independent buffers, and each buffer output can be controlled by its own active-low OE input for 3-state operation.
What supply voltage range is recommended for SN74HC125 operation?
The recommended supply voltage is 2 V minimum, 5 V nominal, and 6 V maximum over the operating free-air temperature range. The specified input and output voltage ranges are both 0 V to VCC.
How fast is the SN74HC125 at a 4.5 V supply?
For A-to-Y propagation at VCC = 4.5 V and CL = 50 pF, the SN74HC125 is specified at 14 ns typical, 24 ns maximum at 25°C, and 36 ns maximum over -40°C to 85°C.
Which package options are listed for the SN74HC125?
Listed package cases include SOIC-14, SSOP-14, PDIP-14, SO-14, TSSOP-14, CDIP-14, and LCCC-20, with dimensions ranging from 5.00 mm x 4.40 mm for TSSOP-14 to 21.30 mm x 7.60 mm for CDIP-14.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 13, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.