Specifications
| Type | Description |
|---|---|
| Part Number | SN74HC373 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Component Type | Other |
| Package Case | 20-pin SOIC DW 12.80 mm x 7.50 mm; SSOP DB 7.20 mm x 5.30 mm; PDIP N 25.40 mm x 6.35 mm; SOP NS 15.00 mm x 5.30 mm; TSSOP PW 6.50 mm x 4.40 mm; CDIP J 26.92 mm x 6.92 mm; LCCC FK 8.89 mm x 8.45 mm; CFP W 13.72 mm x 6.92 mm |
| Function | 8-bit transparent D-type latch with 3-state outputs |
| Operating Supply Voltage | 2 V min, 5 V nom, 6 V max |
| Absolute Maximum Supply Voltage | -0.5 V to 7 V |
| Input Clamp Current | +/-20 mA max; VI < 0 or VI > VCC |
| Output Clamp Current | +/-20 mA max; VO < 0 or VO > VCC |
| Continuous Output Current | +/-35 mA max; VO = 0 V to VCC |
| Continuous Current Through VCC or GND | +/-70 mA max |
| Junction Temperature | 150 °C max |
| Storage Temperature | -65 °C to 150 °C |
| Operating Free-Air Temperature | -55 °C to 125 °C |
| High-Level Input Voltage | 1.5 V min at VCC=2 V; 3.15 V min at VCC=4.5 V; 4.2 V min at VCC=6 V |
| Low-Level Input Voltage | 0.5 V max at VCC=2 V; 1.35 V max at VCC=4.5 V; 1.8 V max at VCC=6 V |
| Input Voltage Range | 0 V to VCC |
| Output Voltage Range | 0 V to VCC |
| Input Transition Rise and Fall Time | 1000 ns max at VCC=2 V; 500 ns max at VCC=4.5 V; 400 ns max at VCC=6 V |
| High-Level Output Voltage | 1.9 V min, 1.998 V typ at VCC=2 V; 4.4 V min, 4.499 V typ at VCC=4.5 V; 5.9 V min, 5.999 V typ at VCC=6 V; IOH=-20 µA |
| High-Level Output Voltage | 3.98 V min, 4.3 V typ at TA=25°C; 3.7 V min over temperature; VCC=4.5 V, IOH=-6 mA |
| High-Level Output Voltage | 5.48 V min, 5.8 V typ at TA=25°C; 5.2 V min over temperature; VCC=6 V, IOH=-7.8 mA |
| Low-Level Output Voltage | 0.002 V typ, 0.1 V max at VCC=2 V; 0.001 V typ, 0.1 V max at VCC=4.5 V; 0.001 V typ, 0.1 V max at VCC=6 V; IOL=20 µA |
| Low-Level Output Voltage | 0.17 V typ, 0.26 V max at TA=25°C; 0.4 V max over temperature; VCC=4.5 V, IOL=6 mA |
| Low-Level Output Voltage | 0.15 V typ, 0.26 V max at TA=25°C; 0.4 V max over temperature; VCC=6 V, IOL=7.8 mA |
| Input Current | +/-0.1 nA typ, +/-1000 nA max for SN74HC373; VCC=6 V, VI=VCC or 0 V |
| Off-State Output Current | +/-0.01 µA typ, +/-10 µA max; VCC=6 V, VO=VCC or 0 V |
| Supply Current | 8 µA typ, 160 µA max; VCC=6 V, VI=VCC or 0 V, IO=0 |
| Input Capacitance | 3 pF typ, 10 pF max; VCC=2 V to 6 V |
| LE High Pulse Duration | 80 ns min at VCC=2 V; 16 ns min at VCC=4.5 V; 14 ns min at VCC=6 V |
| Data Setup Time Before LE Falling Edge | 50 ns min at VCC=2 V; 10 ns min at VCC=4.5 V; 9 ns min at VCC=6 V |
| Data Hold Time After LE Falling Edge | 20 ns min at VCC=2 V; 10 ns min at VCC=4.5 V; 10 ns min at VCC=6 V |
| Propagation Delay D to Q | 58 ns typ, 225 ns max at VCC=2 V; 15 ns typ, 45 ns max at VCC=4.5 V; 13 ns typ, 38 ns max at VCC=6 V; CL=50 pF |
| Propagation Delay LE to Q | 73 ns typ, 265 ns max at VCC=2 V; 18 ns typ, 53 ns max at VCC=4.5 V; 15 ns typ, 45 ns max at VCC=6 V; CL=50 pF |
| Output Enable Time OE to Q | 65 ns typ, 225 ns max at VCC=2 V; 17 ns typ, 45 ns max at VCC=4.5 V; 14 ns typ, 38 ns max at VCC=6 V; CL=50 pF |
| Output Disable Time OE to Q | 50 ns typ, 225 ns max at VCC=2 V; 15 ns typ, 45 ns max at VCC=4.5 V; 13 ns typ, 38 ns max at VCC=6 V; CL=50 pF |
| Output Transition Time | 28 ns typ, 90 ns max at VCC=2 V; 8 ns typ, 18 ns max at VCC=4.5 V; 6 ns typ, 15 ns max at VCC=6 V; CL=50 pF |
| Propagation Delay D to Q | 82 ns typ, 300 ns max at VCC=2 V; 22 ns typ, 60 ns max at VCC=4.5 V; 19 ns typ, 51 ns max at VCC=6 V; CL=150 pF |
| Propagation Delay LE to Q | 100 ns typ, 335 ns max at VCC=2 V; 24 ns typ, 67 ns max at VCC=4.5 V; 20 ns typ, 57 ns max at VCC=6 V; CL=150 pF |
| Output Enable Time OE to Q | 90 ns typ, 300 ns max at VCC=2 V; 23 ns typ, 60 ns max at VCC=4.5 V; 19 ns typ, 51 ns max at VCC=6 V; CL=150 pF |
| Output Transition Time | 45 ns typ, 315 ns max at VCC=2 V; 17 ns typ, 63 ns max at VCC=4.5 V; 13 ns typ, 53 ns max at VCC=6 V; CL=150 pF |
| Power Dissipation Capacitance Per Latch | 100 pF typ; no load, TA=25°C |
| Latch Functional Mode | Q follows D when OE=L and LE=H |
| Latch Hold Mode | Q holds previous state when OE=L and LE=L; at startup Q0 is unknown |
| High-Impedance Output Mode | Q=Z when OE=H; LE and D do not care |
| Datasheet Status | request_only |
Product Overview
The device is specified for 2 V to 6 V recommended supply operation with 5 V nominal operation. Input and output voltage ranges are 0 V to VCC. Recommended input thresholds include VIH of 1.5 V at 2 V, 3.15 V at 4.5 V, and 4.2 V at 6 V, with corresponding VIL limits of 0.5 V, 1.35 V, and 1.8 V.
Key Features
- 8-bit transparent D-type latch with 3-state outputs
- 2 V to 6 V recommended supply operation
- OE high places Q outputs in high impedance
- LE high with OE low makes Q follow D
- LE low with OE low holds previous Q state
- 0 V to VCC input and output voltage ranges
- -55 °C to 125 °C operating free-air temperature
- 3 pF typical input capacitance at 2 V to 6 V
- 8 µA typical supply current at VCC=6 V
- 100 pF typical power dissipation capacitance per latch
Typical Applications
- 8-bit data latch stages
- Three-state output bus control
- Parallel logic state holding
- LE-controlled register interfaces
- CMOS signal-chain logic paths
- Output-enable controlled data isolation
Procurement Notes
When requesting a quote for SN74HC373, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What function does the SN74HC373 provide?
The SN74HC373 is specified as an 8-bit transparent D-type latch with 3-state outputs. With OE low and LE high, Q follows D. With OE low and LE low, Q holds the previous state.
What supply voltage range is recommended?
The recommended operating supply range for the SN74HC373 is 2 V minimum, 5 V nominal, and 6 V maximum. The absolute maximum supply voltage rating is -0.5 V to 7 V.
How does the high-impedance output mode work?
The function table specifies Q equals Z when OE is high. In this high-impedance output mode, LE and D are don't-care inputs according to the extracted datasheet facts.
What packages are listed for this device?
Listed packages include 20-pin SOIC DW, SSOP DB, PDIP N, SOP NS, TSSOP PW, CDIP J, LCCC FK, and CFP W, with dimensions provided for each package case.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 13, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.