Specifications
| Type | Description |
|---|---|
| Part Number | SN74LS373 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | N PDIP, DW SOIC, NS SOP; dimensions not provided in excerpt |
| Logic Function | 8-bit transparent D-type latch with 3-state outputs; SN74LS373 device description |
| Output Type | 3-state bus-driving outputs; designed for capacitive or low-impedance bus loads |
| Latch Transparency | Q follows D when C is high; OC low, C high |
| Latch Hold Operation | Output latched when C is low; data captured at level present before C goes low |
| Output Disable Function | Outputs enter high-impedance state; OC high |
| Internal Operation During Output Disable | Latch operation unaffected; OC high, old data retained or new data entered while outputs are off |
| Function Table Output High | Q = H; OC=L, C=H, D=H |
| Function Table Output Low | Q = L; OC=L, C=H, D=L |
| Function Table Latched Output | Q = Q0; OC=L, C=L, D=X |
| Function Table High-Impedance Output | Q = Z; OC=H, C=X, D=X |
| Supply Voltage Absolute Maximum | 7 V; LS devices, voltage with respect to ground |
| Input Voltage Absolute Maximum | 7 V; LS devices |
| Off-State Output Voltage Absolute Maximum | 5.5 V; LS devices |
| Storage Temperature Range | -65°C to 150°C; LS devices |
| Package Thermal Impedance | 58°C/W; DW package, JESD 51-7 |
| Package Thermal Impedance | 69°C/W; N package, JESD 51-7 |
| Package Thermal Impedance | 60°C/W; NS package, JESD 51-7 |
| Recommended Supply Voltage | Min 4.75 V, Nom 5 V, Max 5.25 V; SN74LS series |
| Recommended High-Level Output Voltage | Max 5.5 V; SN74LS series |
| Recommended High-Level Output Current | -2.6 mA; SN74LS series |
| Recommended Low-Level Output Current | 24 mA; SN74LS series |
| Clock High Pulse Duration | Min 15 ns; SN74LS series |
| Clock Low Pulse Duration | Min 15 ns; SN74LS series |
| Data Setup Time | Min 5 ns; SN74LS373, referenced to C falling edge |
| Data Hold Time | Min 20 ns; SN74LS373, referenced to C falling edge |
| Operating Free-Air Temperature | 0°C to 70°C; SN74LS series |
| High-Level Input Voltage | Min 2 V; SN74LS, recommended operating temperature range |
| Low-Level Input Voltage | Max 0.8 V; SN74LS, recommended operating temperature range |
| Input Clamp Voltage | Max -1.5 V; VCC=MIN, II=-18 mA |
| High-Level Output Voltage | Min 2.4 V, Typ 3.1 V; VCC=MIN, VIH=2 V, VIL=VIL max, IOH=MAX |
| Low-Level Output Voltage | Typ 0.25 V, Max 0.4 V; VCC=MIN, VIH=2 V, VIL=VIL max, IOL=12 mA |
| Low-Level Output Voltage | Typ 0.35 V, Max 0.5 V; VCC=MIN, VIH=2 V, VIL=VIL max, IOL=24 mA |
| Off-State Output Current High-Level Applied | Max 20 uA; VCC=MAX, VIH=2 V, VO=2.7 V |
| Off-State Output Current Low-Level Applied | Max -20 uA; VCC=MAX, VIH=2 V, VO=0.4 V |
| Input Current at Maximum Input Voltage | Max 0.1 mA; VCC=MAX, VI=7 V |
| High-Level Input Current | Max 20 uA; VCC=MAX, VI=2.7 V |
| Low-Level Input Current | Max -0.4 mA; VCC=MAX, VI=0.4 V |
| Short-Circuit Output Current | Min -30 mA, Max -130 mA; VCC=MAX, not more than one output shorted for <=1 s |
| Supply Current | Typ 24 mA, Max 40 mA; SN74LS373, VCC=MAX, output control at 4.5 V |
| Data-to-Q Propagation Delay Low-to-High | Typ 12 ns, Max 18 ns; VCC=5 V, TA=25°C, RL=667 ohm, CL=45 pF |
| Data-to-Q Propagation Delay High-to-Low | Typ 12 ns, Max 18 ns; VCC=5 V, TA=25°C, RL=667 ohm, CL=45 pF |
| C-to-Q Propagation Delay Low-to-High | Typ 20 ns, Max 30 ns; VCC=5 V, TA=25°C, RL=667 ohm, CL=45 pF |
| C-to-Q Propagation Delay High-to-Low | Typ 18 ns, Max 30 ns; VCC=5 V, TA=25°C, RL=667 ohm, CL=45 pF |
| OC Output Enable Time to High Level | Typ 15 ns, Max 28 ns; VCC=5 V, TA=25°C, RL=667 ohm, CL=45 pF |
| OC Output Enable Time to Low Level | Typ 25 ns, Max 36 ns; VCC=5 V, TA=25°C, RL=667 ohm, CL=45 pF |
| OC Output Disable Time from High Level | Typ 15 ns, Max 25 ns; VCC=5 V, TA=25°C, RL=667 ohm, CL=5 pF |
| OC Output Disable Time from Low Level | Typ 12 ns, Max 20 ns; VCC=5 V, TA=25°C, RL=667 ohm, CL=5 pF |
| Datasheet Status | request_only |
Product Overview
The SN74LS373 is a Texas Instruments octal transparent D-type latch with 3-state outputs. Its functional behavior is defined by output control, clock, and data inputs: with OC low and C high, the latch is transparent and Q follows D; with OC low and C low, the output holds the previously captured Q0 state. With OC high, outputs enter the high-impedance state while latch operation continues internally, allowing stored data to be retained or new data to be entered while the outputs are disabled.
Electrical operation is specified for the SN74LS series with a recommended 4.75 V to 5.25 V supply and 0°C to 70°C free-air operating range. Logic thresholds include 2 V minimum high-level input voltage and 0.8 V maximum low-level input voltage. Output drive recommendations include -2.6 mA high-level output current and 24 mA low-level output current.
Package options listed in the excerpt are N PDIP, DW SOIC, and NS SOP. Thermal impedance is 69°C/W for N, 58°C/W for DW, and 60°C/W for NS under JESD 51-7. The 3-state bus-driving outputs support capacitive or low-impedance bus-load applications.
Key Features
- 8-bit transparent D-type latch with 3-state outputs
- Bus-driving outputs for capacitive or low-impedance loads
- Q follows D when OC is low and C is high
- Output holds Q0 when OC is low and C is low
- Outputs enter high impedance when OC is high
- Latch operation continues while outputs are disabled
- Recommended 4.75 V to 5.25 V supply range
- 0°C to 70°C operating free-air temperature range
- 15 ns minimum clock high and low pulse durations
- 5 ns setup and 20 ns hold to C falling edge
- Typ 12 ns data-to-Q propagation delay at 5 V
- N PDIP, DW SOIC, and NS SOP package options
Typical Applications
- 3-state bus interfaces
- Capacitive bus load driving
- Low-impedance bus load driving
- 8-bit data latching
- Transparent data storage
- Output-disabled data retention
- 5 V LS logic systems
Procurement Notes
When requesting a quote for SN74LS373, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of logic function does the SN74LS373 provide?
The SN74LS373 is an octal transparent D-type latch. It provides 8-bit latch operation with 3-state bus-driving outputs intended for capacitive or low-impedance bus loads.
How does the SN74LS373 latch data?
When output control is low and C is high, Q follows the D input. When C goes low, the output holds the data level present before the falling edge, so Q remains at Q0.
What happens when output control is high?
When OC is high, the SN74LS373 outputs enter the high-impedance state. The latch operation is unaffected, so old data can be retained or new data can be entered while outputs are off.
What supply range is recommended for SN74LS373 operation?
For the SN74LS series, the recommended supply voltage is 4.75 V minimum, 5 V nominal, and 5.25 V maximum, with operation specified over 0°C to 70°C free-air temperature.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.