Specifications
| Type | Description |
|---|---|
| Part Number | SN74LS374 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 20-pin DB SSOP, DW SOIC, N PDIP, or NS SOP |
| Logic function | 8-bit positive-edge-triggered D-type flip-flops with 3-state outputs; SN74LS374 device description |
| Output control behavior | OC high places outputs in high-impedance state; Function table: OC=H, CLK=X, D=X |
| Clock triggering | Q follows D on positive transition of CLK; Function table: OC=L, CLK rising edge |
| Output hold behavior | Q0 retained; Function table: OC=L, CLK=L, D=X |
| Supply voltage | 4.75 V min, 5 V nom, 5.25 V max; SN74LS recommended operating conditions |
| Operating free-air temperature | 0°C to 70°C; SN74LS recommended operating conditions |
| High-level output voltage rating | 5.5 V max; SN74LS recommended operating conditions, VOH |
| High-level output current | -2.6 mA max; SN74LS recommended operating conditions, IOH |
| Low-level output current | 24 mA max; SN74LS recommended operating conditions, IOL |
| Clock high pulse duration | 15 ns min; SN74LS374 recommended operating conditions |
| Clock low pulse duration | 15 ns min; SN74LS374 recommended operating conditions |
| Data setup time | 20 ns min; SN74LS374, setup to CLK rising edge |
| Data hold time | 0 ns min; SN74LS374 commercial, hold after CLK rising edge; below 10 MHz note applies |
| High-level input voltage | 2 V min; SN74LS electrical characteristics |
| Low-level input voltage | 0.8 V max; SN74LS electrical characteristics |
| Input clamp voltage | -1.5 V max; VCC=min, II=-18 mA |
| High-level output voltage | 2.4 V min, 3.1 V typ; VCC=min, VIH=2 V, VIL=VIL max, IOH=max |
| Low-level output voltage at 12 mA | 0.25 V typ, 0.4 V max; VCC=min, VIH=2 V, VIL=VIL max, IOL=12 mA |
| Low-level output voltage at 24 mA | 0.35 V typ, 0.5 V max; VCC=min, VIH=2 V, VIL=VIL max, IOL=24 mA |
| Off-state high-level output current | 20 µA max; VCC=max, VIH=2 V, VO=2.7 V |
| Off-state low-level output current | -20 µA max; VCC=max, VIH=2 V, VO=0.4 V |
| Input current at maximum input voltage | 0.1 mA max; VCC=max, VI=7 V |
| High-level input current | 20 µA max; VCC=max, VI=2.7 V |
| Low-level input current | -0.4 mA max; VCC=max, VI=0.4 V |
| Short-circuit output current | -30 mA min, -130 mA max; VCC=max; not more than one output shorted for up to 1 s |
| Supply current | 27 mA typ, 40 mA max; SN74LS374, VCC=max, output control at 4.5 V |
| Maximum clock frequency | 35 MHz min, 50 MHz typ; VCC=5 V, TA=25°C, RL=667 ohm, CL=45 pF, all outputs loaded |
| Clock-to-output propagation delay low-to-high | 15 ns typ, 28 ns max; CLK to any Q, VCC=5 V, TA=25°C, RL=667 ohm, CL=45 pF |
| Clock-to-output propagation delay high-to-low | 19 ns typ, 28 ns max; CLK to any Q, VCC=5 V, TA=25°C, RL=667 ohm, CL=45 pF |
| Output enable time to high level | 20 ns typ, 26 ns max; OC to any Q, VCC=5 V, TA=25°C, RL=667 ohm, CL=45 pF |
| Output enable time to low level | 21 ns typ, 28 ns max; OC to any Q, VCC=5 V, TA=25°C, RL=667 ohm, CL=45 pF |
| Output disable time from high level | 15 ns typ, 28 ns max; OC to any Q, VCC=5 V, TA=25°C, RL=667 ohm, CL=5 pF |
| Output disable time from low level | 12 ns typ, 20 ns max; OC to any Q, VCC=5 V, TA=25°C, RL=667 ohm, CL=5 pF |
| Absolute maximum supply voltage | 7 V; LS devices, over operating free-air temperature range |
| Absolute maximum input voltage | 7 V; LS devices, over operating free-air temperature range |
| Absolute maximum off-state output voltage | 5.5 V; LS devices, over operating free-air temperature range |
| Storage temperature range | -65°C to 150°C; LS devices absolute maximum ratings |
| Package thermal impedance, DB package | 70°C/W; DB package, JESD 51-7 |
| Package thermal impedance, DW package | 58°C/W; DW package, JESD 51-7 |
| Package thermal impedance, N package | 69°C/W; N package, JESD 51-7 |
| Package thermal impedance, NS package | 60°C/W; NS package, JESD 51-7 |
| Datasheet Status | request_only |
Product Overview
The SN74LS374 is a Texas Instruments octal D-type flip-flop for Signal_Chain designs requiring 8-bit positive-edge-triggered storage with 3-state outputs. According to the function table, Q follows D on the positive transition of CLK when output control is low, while Q0 is retained when output control is low and CLK is low. When OC is high, the outputs are placed in the high-impedance state.
Recommended operation is centered on a 5 V nominal supply, with a 4.75 V minimum and 5.25 V maximum range. The commercial operating free-air temperature range is 0°C to 70°C. Input thresholds are specified at 2 V minimum high-level input voltage and 0.8 V maximum low-level input voltage.
Timing data includes a 35 MHz minimum and 50 MHz typical maximum clock frequency under the stated 5 V, 25°C, RL=667 ohm, CL=45 pF test condition. Clock-to-output propagation delay is specified at 15 ns typical and 28 ns maximum low-to-high, and 19 ns typical and 28 ns maximum high-to-low. Package options include 20-pin DB SSOP, DW SOIC, N PDIP, and NS SOP.
Key Features
- 8-bit positive-edge-triggered D-type flip-flop logic
- 3-state outputs controlled by OC input
- OC high places outputs in high-impedance state
- Q follows D on CLK positive transition
- Q0 retained when OC low and CLK low
- 4.75 V to 5.25 V recommended supply range
- 0°C to 70°C operating free-air temperature
- 35 MHz minimum maximum clock frequency
- 15 ns minimum clock high and low pulse durations
- 20 ns minimum setup time to CLK rising edge
- 20-pin DB, DW, N, or NS package options
Typical Applications
- 8-bit data registers
- Tri-state bus interfaces
- Clocked data storage
- Parallel logic buffering
- TTL signal-chain control
- Output-enable controlled data paths
Procurement Notes
When requesting a quote for SN74LS374, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What logic function does the SN74LS374 provide?
The SN74LS374 provides 8-bit positive-edge-triggered D-type flip-flops with 3-state outputs. With OC low, Q follows D on the rising edge of CLK, while Q0 is retained when CLK is low.
What happens when OC is high on the SN74LS374?
The function table specifies that when OC is high, with CLK and D as don't-care inputs, the SN74LS374 outputs are placed in the high-impedance state.
What supply and temperature range are specified?
The recommended supply voltage range is 4.75 V minimum, 5 V nominal, and 5.25 V maximum. The specified operating free-air temperature range for the SN74LS device is 0°C to 70°C.
What timing parameters define clocked operation?
The SN74LS374 has 15 ns minimum clock high and low pulse durations, 20 ns minimum data setup time to the CLK rising edge, and 0 ns minimum data hold time after the rising edge for the commercial condition.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.