Specifications
| Type | Description |
|---|---|
| Part Number | SN74LVC2G125 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | SM8 (DCT) 2.95 mm x 2.80 mm; VSSOP (DCU) 2.30 mm x 2.00 mm; DSBGA (YZP) 1.91 mm x 0.91 mm |
| Logic Function | Dual bus buffer gate with 3-state outputs; outputs disabled when associated OE input is high |
| Supply Voltage Range | 1.65-5.5 V; recommended operating condition |
| Data Retention Supply Voltage | 1.5 V min; data retention only |
| Input Voltage Range | 0-5.5 V; recommended operating condition |
| Output Voltage Range | 0-VCC; output in high or low state |
| Output Voltage Range | 0-5.5 V; output in 3-state mode |
| High-Level Input Voltage | 0.65 x VCC min; VCC=1.65 V to 1.95 V |
| High-Level Input Voltage | 1.7 V min; VCC=2.3 V to 2.7 V |
| High-Level Input Voltage | 2.0 V min; VCC=3.0 V to 3.6 V |
| High-Level Input Voltage | 0.7 x VCC min; VCC=4.5 V to 5.5 V |
| Low-Level Input Voltage | 0.35 x VCC max; VCC=1.65 V to 1.95 V |
| Low-Level Input Voltage | 0.7 V max; VCC=2.3 V to 2.7 V |
| Low-Level Input Voltage | 0.8 V max; VCC=3.0 V to 3.6 V |
| Low-Level Input Voltage | 0.3 x VCC max; VCC=4.5 V to 5.5 V |
| High-Level Output Current | -24 mA; VCC=3 V |
| Low-Level Output Current | 24 mA; VCC=3 V |
| Maximum Propagation Delay | 4.3 ns max; A to Y, VCC=3.3 V ±0.3 V, TA=-40°C to +85°C |
| Output Enable Time | 1.2-4.7 ns; OE to Y, VCC=3.3 V ±0.3 V, TA=-40°C to +85°C |
| Output Disable Time | 1.4-4.6 ns; OE to Y, VCC=3.3 V ±0.3 V, TA=-40°C to +85°C |
| Operating Free-Air Temperature | -40°C to +125°C; recommended operating condition |
| Maximum ICC | 10 µA max; VI=5.5 V or GND, IO=0, VCC=1.65 V to 5.5 V |
| Power-Off Leakage Current | ±10 µA max; VI or VO=5.5 V, VCC=0 V |
| Input Leakage Current | ±5 µA max; A or OE inputs, VI=5.5 V or GND, VCC=0 V to 5.5 V |
| High-Impedance Output Leakage Current | 10 µA max; VO=0 V to 5.5 V, VCC=3.6 V |
| ESD Rating HBM | 2000 V; human-body model per ANSI/ESDA/JEDEC JS-001 |
| ESD Rating CDM | 1000 V; charged-device model per JEDEC JESD22-C101 |
| Absolute Maximum Supply Voltage | -0.5 V to 6.5 V; stress rating only |
| Absolute Maximum Input Voltage | -0.5 V to 6.5 V; stress rating only |
| Continuous Output Current | ±50 mA; absolute maximum rating |
| Latch-Up Performance | Exceeds 100 mA; per JESD78 Class II |
| Datasheet Status | request_only |
Product Overview
The SN74LVC2G125 is a Texas Instruments dual bus buffer gate with 3-state outputs for Signal_Chain designs that need controlled digital signal buffering. Each output is disabled when its associated OE input is high, allowing the output node to enter a high-impedance state when required by the system interface.
Recommended operation spans a 1.65 V to 5.5 V supply range, with 1.5 V minimum supply for data retention only. Inputs support 0 V to 5.5 V, outputs support 0 V to VCC in the high or low state, and outputs tolerate 0 V to 5.5 V in 3-state mode. At VCC = 3 V, the device supports -24 mA high-level output current and 24 mA low-level output current.
Package options include SM8 (DCT), VSSOP (DCU), and DSBGA (YZP), supporting compact assembly formats. Timing specifications include 4.3 ns maximum A-to-Y propagation delay, 1.2 ns to 4.7 ns output enable time, and 1.4 ns to 4.6 ns output disable time at VCC = 3.3 V ±0.3 V over -40°C to +85°C.
Key Features
- Dual bus buffer gate with 3-state outputs
- Outputs disable when associated OE input is high
- 1.65 V to 5.5 V recommended supply range
- 0 V to 5.5 V recommended input voltage range
- Outputs support 0 V to VCC in active state
- 3-state outputs tolerate 0 V to 5.5 V
- 4.3 ns maximum A-to-Y propagation delay at 3.3 V
- -24 mA and 24 mA output current at 3 V
- 10 µA maximum ICC across 1.65 V to 5.5 V
- -40°C to +125°C operating free-air temperature
- 2000 V HBM and 1000 V CDM ESD ratings
- Latch-up performance exceeds 100 mA per JESD78 Class II
Typical Applications
- 3-state digital bus buffering
- Output-enable controlled signal gating
- Mixed-voltage digital interfaces
- Compact logic signal buffering
- High-impedance output isolation
- Low-power logic signal paths
- Temperature-rated control interfaces
Procurement Notes
When requesting a quote for SN74LVC2G125, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is the SN74LVC2G125?
The SN74LVC2G125 is a Texas Instruments dual bus buffer gate with 3-state outputs. Each output is disabled when the associated OE input is high, placing that output in a high-impedance state.
What supply voltage range does SN74LVC2G125 support?
The recommended operating supply voltage range is 1.65 V to 5.5 V. The datasheet facts also specify a 1.5 V minimum supply voltage for data retention only.
What are the SN74LVC2G125 timing specifications at 3.3 V?
At VCC = 3.3 V ±0.3 V and TA = -40°C to +85°C, A-to-Y propagation delay is 4.3 ns maximum, output enable time is 1.2 ns to 4.7 ns, and output disable time is 1.4 ns to 4.6 ns.
Which package options are listed for SN74LVC2G125?
The listed package options are SM8 (DCT) measuring 2.95 mm x 2.80 mm, VSSOP (DCU) measuring 2.30 mm x 2.00 mm, and DSBGA (YZP) measuring 1.91 mm x 0.91 mm.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.