Specifications
| Type | Description |
|---|---|
| Part Number | SN74LVC2G17 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Component Type | Other |
| Package Case | SOT-23(6) 2.90 mm x 1.60 mm; SC70(6) 2.00 mm x 1.25 mm; SON(6) 1.45 mm x 1.00 mm; SON(6) 1.00 mm x 1.00 mm; DSBGA(6) 1.41 mm x 0.91 mm |
| Logic function | Y = A; condition: Two independent non-inverting Schmitt-trigger buffers; source page: 1 |
| Number of buffers | 2; condition: Device contains two buffers; source page: 1 |
| Supply voltage range | 1.65 to 5.5 V; condition: Recommended operating conditions; source page: 4 |
| Input voltage range | 0 to 5.5 V; condition: Recommended operating conditions; source page: 4 |
| Output voltage range | 0 to VCC; condition: Recommended operating conditions; source page: 4 |
| Operating free-air temperature | -40 to 125 °C; condition: Recommended operating conditions; source page: 4 |
| High-level output current | -4 mA; condition: VCC=1.65 V; source page: 4 |
| High-level output current | -8 mA; condition: VCC=2.3 V; source page: 4 |
| High-level output current | -24 mA; condition: VCC=3 V; source page: 4 |
| High-level output current | -32 mA; condition: VCC=4.5 V; source page: 4 |
| Low-level output current | 4 mA; condition: VCC=1.65 V; source page: 4 |
| Low-level output current | 8 mA; condition: VCC=2.3 V; source page: 4 |
| Low-level output current | 24 mA; condition: VCC=3 V; source page: 4 |
| Low-level output current | 32 mA; condition: VCC=4.5 V; source page: 4 |
| Absolute maximum supply voltage | -0.5 to 6.5 V; condition: Over operating free-air temperature range unless noted; source page: 4 |
| Absolute maximum input voltage | -0.5 to 6.5 V; condition: Input voltage range; source page: 4 |
| Absolute maximum output voltage, high-impedance or power-off | -0.5 to 6.5 V; condition: Applied to any output in high-impedance or power-off state; source page: 4 |
| Absolute maximum output voltage, high or low state | -0.5 to VCC + 0.5 V; condition: Applied to any output in high or low state; source page: 4 |
| Input clamp current | -50 mA; condition: VI < 0; source page: 4 |
| Output clamp current | -50 mA; condition: VO < 0; source page: 4 |
| Continuous output current | ±50 mA; condition: Absolute maximum rating; source page: 4 |
| Continuous current through VCC or GND | ±100 mA; condition: Absolute maximum rating; source page: 4 |
| Junction temperature under bias | 150 °C; condition: Absolute maximum rating; source page: 4 |
| Storage temperature range | -65 to 150 °C; condition: Absolute maximum rating; source page: 4 |
| ESD rating, Human-Body Model | 2000 V; condition: Per ANSI/ESDA/JEDEC JS-001, all pins; source page: 4 |
| ESD rating, Charged-Device Model | 1000 V; condition: Per JEDEC JESD22-C101, all pins; source page: 4 |
| Junction-to-ambient thermal resistance | 165 °C/W; condition: DBV package, 6 pins, JESD51-7; source page: 5 |
| Junction-to-ambient thermal resistance | 259 °C/W; condition: DCK package, 6 pins, JESD51-7; source page: 5 |
| Junction-to-ambient thermal resistance | 123 °C/W; condition: YZP package, 6 pins, JESD51-7; source page: 5 |
| Junction-to-ambient thermal resistance | 234 °C/W; condition: DRY package, 6 pins, JESD51-7; source page: 5 |
| Junction-to-ambient thermal resistance | 300 °C/W; condition: DSF package, 6 pins, JESD51-7; source page: 5 |
| Positive-going input threshold voltage VT+ | 0.7 to 1.4 V; condition: VCC=1.65 V, -40°C to 125°C; source page: 5 |
| Positive-going input threshold voltage VT+ | 1.0 to 1.7 V; condition: VCC=2.3 V, -40°C to 125°C; source page: 5 |
| Positive-going input threshold voltage VT+ | 1.3 to 2.0 V; condition: VCC=3 V, -40°C to 125°C; source page: 5 |
| Positive-going input threshold voltage VT+ | 1.9 to 3.1 V; condition: VCC=4.5 V, -40°C to 125°C; source page: 5 |
| Positive-going input threshold voltage VT+ | 2.2 to 3.7 V; condition: VCC=5.5 V, -40°C to 125°C; source page: 5 |
| Negative-going input threshold voltage VT- | 0.3 to 0.7 V; condition: VCC=1.65 V, -40°C to 125°C; source page: 5 |
| Negative-going input threshold voltage VT- | 0.4 to 1.0 V; condition: VCC=2.3 V, -40°C to 125°C; source page: 5 |
| Negative-going input threshold voltage VT- | 0.8 to 1.3 V; condition: VCC=3 V, -40°C to 125°C; source page: 5 |
| Negative-going input threshold voltage VT- | 1.1 to 2.0 V; condition: VCC=4.5 V, -40°C to 125°C; source page: 5 |
| Negative-going input threshold voltage VT- | 1.4 to 2.5 V; condition: VCC=5.5 V, -40°C to 125°C; source page: 5 |
| Input hysteresis ΔVT | 0.3 to 0.8 V; condition: VCC=1.65 V, -40°C to 125°C; source page: 5 |
| Input hysteresis ΔVT | 0.35 to 0.9 V; condition: VCC=2.3 V, -40°C to 125°C; source page: 5 |
| Input hysteresis ΔVT | 0.4 to 1.1 V; condition: VCC=3 V, -40°C to 125°C; source page: 5 |
| Input hysteresis ΔVT | 0.6 to 1.3 V; condition: VCC=4.5 V, -40°C to 125°C; source page: 5 |
| Input hysteresis ΔVT | 0.7 to 1.4 V; condition: VCC=5.5 V, -40°C to 125°C; source page: 5 |
| High-level output voltage VOH | VCC - 0.1 V min; condition: IOH=-100 µA, VCC=1.65 V to 5.5 V; source page: 5 |
| High-level output voltage VOH | 1.2 V min; condition: IOH=-4 mA, VCC=1.65 V; source page: 5 |
| High-level output voltage VOH | 1.9 V min; condition: IOH=-8 mA, VCC=2.3 V; source page: 5 |
| High-level output voltage VOH | 2.4 V min; condition: IOH=-16 mA, VCC=3 V; source page: 5 |
| High-level output voltage VOH | 2.3 V min; condition: IOH=-24 mA, VCC=3 V; source page: 5 |
| High-level output voltage VOH | 3.8 V min; condition: IOH=-32 mA, VCC=4.5 V; source page: 5 |
| Low-level output voltage VOL | 0.1 V max; condition: IOL=100 µA, VCC=1.65 V to 5.5 V; source page: 5 |
| Low-level output voltage VOL | 0.45 V max; condition: IOL=4 mA, VCC=1.65 V; source page: 5 |
| Low-level output voltage VOL | 0.3 V max; condition: IOL=8 mA, VCC=2.3 V; source page: 5 |
| Low-level output voltage VOL | 0.4 V max; condition: IOL=16 mA, VCC=3 V; source page: 5 |
| Low-level output voltage VOL | 0.55 V max; condition: IOL=24 mA, VCC=3 V; source page: 5 |
| Low-level output voltage VOL | 0.55 V max; condition: IOL=32 mA, VCC=4.5 V; source page: 5 |
| Input current II | ±5 µA max; condition: A input, VI=5.5 V or GND, VCC=0 to 5.5 V, -40°C to 125°C; source page: 5 |
| Power-off leakage current Ioff | ±10 µA max; condition: VI or VO=5.5 V, VCC=0 V, -40°C to 125°C; source page: 5 |
| Supply current ICC | 10 µA max; condition: VI=5.5 V or GND, IO=0, VCC=1.65 V to 5.5 V, -40°C to 125°C; source page: 5 |
| Delta supply current ΔICC | 500 µA max; condition: One input at VCC - 0.6 V, other inputs at VCC or GND, VCC=3 V to 5.5 V, -40°C to 125°C; source page: 5 |
| Input capacitance Ci | 4 pF typ; condition: VI=VCC or GND, VCC=3.3 V, TA=25°C; source page: 5 |
| Propagation delay tpd | 3.9 to 9.3 ns; condition: A to Y, VCC=1.8 V ±0.15 V, -40°C to 85°C; source page: 6 |
| Propagation delay tpd | 1.9 to 5.7 ns; condition: A to Y, VCC=2.5 V ±0.2 V, -40°C to 85°C; source page: 6 |
| Propagation delay tpd | 2.2 to 5.4 ns; condition: A to Y, VCC=3.3 V ±0.3 V, -40°C to 85°C; source page: 6 |
| Propagation delay tpd | 1.5 to 4.3 ns; condition: A to Y, VCC=5 V ±0.5 V, -40°C to 85°C; source page: 6 |
| Propagation delay tpd | 3.9 to 9.8 ns; condition: A to Y, VCC=1.8 V ±0.15 V, -40°C to 125°C; source page: 6 |
| Propagation delay tpd | 1.9 to 6.2 ns; condition: A to Y, VCC=2.5 V ±0.2 V, -40°C to 125°C; source page: 6 |
| Propagation delay tpd | 2.2 to 5.9 ns; condition: A to Y, VCC=3.3 V ±0.3 V, -40°C to 125°C; source page: 6 |
| Propagation delay tpd | 1.5 to 4.8 ns; condition: A to Y, VCC=5 V ±0.5 V, -40°C to 125°C; source page: 6 |
| Power dissipation capacitance Cpd | 17 pF typ; condition: f=10 MHz, VCC=1.8 V, TA=25°C; source page: 6 |
| Power dissipation capacitance Cpd | 18 pF typ; condition: f=10 MHz, VCC=2.5 V, TA=25°C; source page: 6 |
| Power dissipation capacitance Cpd | 19 pF typ; condition: f=10 MHz, VCC=3.3 V, TA=25°C; source page: 6 |
| Power dissipation capacitance Cpd | 21 pF typ; condition: f=10 MHz, VCC=5 V, TA=25°C; source page: 6 |
| Latch-up performance | Exceeds 100 mA; condition: Per JESD78, Class II; source page: 1 |
| Maximum propagation delay feature | 5.4 ns max; condition: VCC=3.3 V; source page: 1 |
| Output drive feature | ±24 mA; condition: VCC=3.3 V; source page: 1 |
| Low power consumption feature | 10 µA max ICC; condition: Feature summary; source page: 1 |
| Input voltage tolerance feature | Inputs accept voltages to 5.5 V; condition: Feature summary; source page: 1 |
| Partial-power-down support | Ioff supports live insertion, partial-power-down mode, and back-drive protection; condition: Ioff circuitry disables outputs when powered down; source page: 1 |
| Pin 1 function | 1A, input 1; condition: Pin functions table; source page: 3 |
| Pin 6 function | 1Y, output 1; condition: Pin functions table; source page: 3 |
| Pin 3 function | 2A, input 2; condition: Pin functions table; source page: 3 |
| Pin 4 function | 2Y, output 2; condition: Pin functions table; source page: 3 |
| Pin 2 function | GND, ground; condition: Pin functions table; source page: 3 |
| Pin 5 function | VCC, power pin; condition: Pin functions table; source page: 3 |
| Datasheet Status | request_only |
Product Overview
The SN74LVC2G17 is a Texas Instruments dual Schmitt-trigger buffer for Signal_Chain applications that need two independent non-inverting buffer paths. Each channel follows the Y = A logic function, with inputs assigned to 1A and 2A and outputs assigned to 1Y and 2Y. Schmitt-trigger thresholds are specified across VCC values from 1.65 V to 5.5 V, with positive-going, negative-going, and hysteresis ranges provided over -40°C to 125°C.
Recommended operation covers a 1.65 V to 5.5 V supply range, 0 V to 5.5 V inputs, and outputs from 0 V to VCC. Electrical limits include 10 µA maximum supply current, ±5 µA maximum input current, ±10 µA maximum power-off leakage current, and 4 pF typical input capacitance at VCC = 3.3 V.
The device is available in compact 6-pin SOT-23, SC70, SON, and DSBGA packages. Ioff circuitry disables outputs when powered down, supporting live insertion, partial-power-down mode, and back-drive protection.
Key Features
- Two independent non-inverting Schmitt-trigger buffers
- Y = A logic function on each channel
- 1.65 V to 5.5 V supply voltage range
- Inputs accept voltages from 0 V to 5.5 V
- -40°C to 125°C operating free-air temperature
- 10 µA maximum ICC across specified supply range
- 5.4 ns maximum propagation delay at 3.3 V
- ±24 mA output drive feature at 3.3 V
- Ioff supports live insertion and back-drive protection
- HBM 2000 V and CDM 1000 V ESD ratings
Typical Applications
- Schmitt-trigger signal buffering
- Non-inverting logic buffering
- Partial-power-down interfaces
- Live insertion support
- Back-drive protection designs
- Low-power signal paths
- 5.5 V-tolerant input designs
- Compact 6-pin board layouts
Procurement Notes
When requesting a quote for SN74LVC2G17, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What logic function does SN74LVC2G17 implement?
SN74LVC2G17 implements Y = A on two independent non-inverting Schmitt-trigger buffer channels. The extracted pin functions identify 1A and 2A as inputs and 1Y and 2Y as the corresponding outputs.
What supply and input voltage ranges are specified?
The recommended supply voltage range is 1.65 V to 5.5 V. The recommended input voltage range is 0 V to 5.5 V, and the output voltage range is specified from 0 V to VCC.
Which package formats are listed for this device?
The listed package options are 6-pin SOT-23 measuring 2.90 mm x 1.60 mm, 6-pin SC70 measuring 2.00 mm x 1.25 mm, 6-pin SON formats, and a 6-pin DSBGA measuring 1.41 mm x 0.91 mm.
Does the device support partial-power-down operation?
Yes. The extracted facts state that Ioff circuitry disables outputs when powered down and supports live insertion, partial-power-down mode, and back-drive protection.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 21, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.