Specifications
| Type | Description |
|---|---|
| Part Number | TLV3502 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | TLV3502: 8-pin SOT-23/DCN 1.63 mm x 2.90 mm; 8-pin SOIC/D 3.91 mm x 4.90 mm |
| Comparator channels | 2; TLV3502 dual device |
| Output stage | Push-pull CMOS; rail-to-rail output drives CMOS or TTL logic |
| Input/output capability | Rail-to-rail I/O; device feature |
| Recommended supply voltage | 2.2 V min, 2.7 V nom, 5.5 V max; recommended operating conditions over operating free-air temperature range |
| Specified supply voltage range | 2.7 V to 5.5 V; TA=25°C unless otherwise noted |
| Operating voltage range | 2.2 V to 5.5 V; TA=25°C unless otherwise noted |
| Absolute maximum supply voltage | 5.5 V max; over operating free-air temperature range unless otherwise noted |
| Signal input terminal voltage | (V-) - 0.3 V min, (V+) + 0.3 V max; absolute maximum rating |
| Signal input terminal current | 10 mA max; absolute maximum rating; input terminals diode-clamped to supply rails |
| Output short-circuit current | 74 mA max; short-circuit to ground, one comparator per package |
| Operating free-air temperature | -40°C to 125°C; recommended operating conditions |
| Junction temperature | 150°C max; absolute maximum rating |
| Storage temperature | -65°C to 150°C; absolute maximum rating |
| ESD rating HBM | ±3000 V; human-body model per ANSI/ESDA/JEDEC JS-001 |
| ESD rating CDM | ±500 V; charged-device model per JEDEC JESD22-C101 |
| Input offset voltage | ±1 mV typ, ±6.5 mV max; VCM=0 V, IO=0 mA, TA=25°C, VS=2.7 V to 5.5 V |
| Input offset voltage temperature drift | ±5 µV/°C typ; TA=-40°C to 125°C |
| Power-supply rejection ratio | 100 µV/V typ, 400 µV/V max; input offset voltage vs power supply, VS=2.7 V to 5.5 V |
| Input hysteresis | 6 mV typ; TA=25°C, VS=2.7 V to 5.5 V unless otherwise noted |
| Input bias current | ±2 pA typ, ±10 pA max; VCM=VCC/2; not production tested |
| Input offset current | ±2 pA typ, ±10 pA max; VCM=VCC/2; difference between IB+ and IB-; not production tested |
| Common-mode voltage range | (V-) - 0.2 V min, (V+) - 0.2 V max; TA=25°C, VS=2.7 V to 5.5 V unless otherwise noted |
| Common-mode rejection ratio | 57 dB min, 70 dB typ; VCM=-0.2 V to (V+) + 0.2 V |
| Common-mode rejection ratio over temperature | 55 dB min; VCM=-0.2 V to (V+) + 0.2 V, TA=-40°C to 125°C |
| Common-mode input impedance | 10^13 Ω || 2 pF; TA=25°C, VS=2.7 V to 5.5 V unless otherwise noted |
| Differential input impedance | 10^13 Ω || 4 pF; TA=25°C, VS=2.7 V to 5.5 V unless otherwise noted |
| Voltage output swing from rail | 30 mV typ, 50 mV max; IOUT=±1 mA |
| Quiescent current | 3.2 mA typ, 5 mA max; VS=5 V, VO=High |
| Propagation delay time | 4.5 ns typ, 6.4 ns max; TA=25°C, ΔVIN=100 mV, overdrive=20 mV |
| Propagation delay time over temperature | 7 ns max; TA=-40°C to 125°C, ΔVIN=100 mV, overdrive=20 mV |
| Propagation delay time low overdrive | 7.5 ns typ, 10 ns max; TA=25°C, ΔVIN=100 mV, overdrive=5 mV |
| Propagation delay time low overdrive over temperature | 12 ns max; TA=-40°C to 125°C, ΔVIN=100 mV, overdrive=5 mV |
| Propagation delay skew | 0.5 ns typ; ΔVIN=100 mV, overdrive=20 mV |
| Maximum toggle frequency | 80 MHz typ; overdrive=50 mV, VS=5 V |
| Rise time | 1.5 ns typ; measured between 10% of VS and 90% of VS |
| Fall time | 1.5 ns typ; measured between 10% of VS and 90% of VS |
| TLV3502 SOIC junction-to-ambient thermal resistance | 116.4°C/W; D package, 8 pins |
| TLV3502 SOT-23 junction-to-ambient thermal resistance | 191.6°C/W; DCN package, 8 pins |
| TLV3502 SOIC junction-to-case top thermal resistance | 61.7°C/W; D package, 8 pins |
| TLV3502 SOT-23 junction-to-case top thermal resistance | 43.9°C/W; DCN package, 8 pins |
| TLV3502 SOIC junction-to-board thermal resistance | 57°C/W; D package, 8 pins |
| TLV3502 SOT-23 junction-to-board thermal resistance | 120.3°C/W; DCN package, 8 pins |
| Datasheet Status | request_only |
Product Overview
The TLV3502 is a Texas Instruments dual high-speed comparator in the Signal_Chain category. The device provides two comparator channels with rail-to-rail input/output capability and a push-pull CMOS output stage intended to drive CMOS or TTL logic levels.
Supply operation is specified across 2.7 V to 5.5 V, with a recommended operating range extending from 2.2 V minimum to 5.5 V maximum. Electrical parameters include ±1 mV typical input offset voltage, 6 mV typical input hysteresis, ±2 pA typical input bias current, and 57 dB minimum common-mode rejection ratio at the stated common-mode condition.
For timing-focused designs, the TLV3502 provides 4.5 ns typical propagation delay at 20 mV overdrive and 7.5 ns typical delay at 5 mV overdrive. It also specifies 0.5 ns typical propagation delay skew, 1.5 ns typical rise and fall times, and 80 MHz typical maximum toggle frequency. Package options include 8-pin SOT-23/DCN and 8-pin SOIC/D formats with documented thermal resistance values.
Key Features
- Dual comparator device with two channels
- Push-pull CMOS output drives CMOS or TTL logic
- Rail-to-rail input and output capability
- Recommended supply range from 2.2 V to 5.5 V
- 4.5 ns typical propagation delay at 20 mV overdrive
- 80 MHz typical maximum toggle frequency at 5 V
- 6 mV typical input hysteresis
- 3.2 mA typical quiescent current at 5 V
- -40°C to 125°C operating free-air temperature
- Available in 8-pin SOT-23 and SOIC packages
Typical Applications
- High-speed threshold detection
- CMOS or TTL logic interfacing
- Rail-to-rail signal comparison
- Low-overdrive comparator timing
- Dual-channel signal monitoring
- 5 V comparator systems
- 2.7 V to 5.5 V signal chains
Procurement Notes
When requesting a quote for TLV3502, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
How many comparator channels does the TLV3502 include?
The TLV3502 is the dual device and includes two comparator channels. It is described as a dual high-speed comparator with rail-to-rail input/output capability and a push-pull CMOS output stage.
What supply voltage range is recommended for TLV3502 operation?
The recommended supply voltage range is 2.2 V minimum, 2.7 V nominal, and 5.5 V maximum over the operating free-air temperature range. Electrical specifications also state a 2.7 V to 5.5 V specified supply range.
What propagation delay is specified for the TLV3502?
At TA=25°C with ΔVIN=100 mV and 20 mV overdrive, propagation delay is 4.5 ns typical and 6.4 ns maximum. Across -40°C to 125°C under the same overdrive condition, the maximum is 7 ns.
Which packages are listed for the TLV3502?
The TLV3502 package information lists an 8-pin SOT-23/DCN package measuring 1.63 mm x 2.90 mm and an 8-pin SOIC/D package measuring 3.91 mm x 4.90 mm.
What output stage does the TLV3502 use?
The TLV3502 uses a push-pull CMOS output stage. The output is described as rail-to-rail and is intended to drive CMOS or TTL logic levels.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: June 30, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.