Specifications
| Type | Description |
|---|---|
| Part Number | TLV704 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Component Type | Power_IC |
| Package / Case | DBV (SOT-23, 5-pin), 2.90 mm x 1.60 mm nominal body size |
| Input Voltage Range | 2.5 V to 24 V; recommended operating conditions; source page 5 |
| Maximum Input Voltage | 30 V max; new chip only, feature summary; source page 1 |
| Fixed Output Voltage Options | 1.8 V to 5 V; available fixed output options; source page 1 |
| Recommended Output Voltage Range | 1.205 V to 5 V; recommended operating conditions; source page 5 |
| Electrical Output Voltage Range | 1.2 V min, 5 V max; TJ = 25°C; source page 6 |
| Output Current | 0 mA to 150 mA; recommended operating conditions; source page 5 |
| Maximum Output Current | Up to 150 mA; feature summary; source page 1 |
| Quiescent Current | 3.4 uA typical; 100-mA load current; source page 1 |
| Ground Pin Current, Legacy, 0 mA | 3.2 uA typ, 4.5 uA max; IOUT = 0 mA, TJ = 25°C; source page 6 |
| Ground Pin Current, Legacy, 100 mA | 3.2 uA typ, 5.5 uA max; IOUT = 100 mA, TJ = 25°C; source page 6 |
| Ground Pin Current, New, 0 mA | 3.2 uA typ, 4.1 uA max; IOUT = 0 mA, TJ = 25°C; source page 6 |
| Ground Pin Current, New, 100 mA | 3.4 uA typ, 4.5 uA max; IOUT = 100 mA, TJ = 25°C; source page 6 |
| Output Capacitor Stability Requirement | >= 0.47 uF effective capacitance; required for stability; source page 3 |
| Recommended Output Capacitor, New Chip | 1 uF nominal; recommended operating conditions, assumed 50% derating; source page 5 |
| Recommended Output Capacitor, Legacy Chip | 0.47 uF to 1 uF; recommended operating conditions; source page 5 |
| Recommended Input Capacitor | 0.047 uF effective; recommended to counteract source resistance and inductance, not required for LDO stability; source page 5 |
| Input Pin Capacitor Recommendation | 0.1 uF or larger; from IN pin to ground; source page 3 |
| Output Pin Capacitor Requirement | 1 uF or larger; from OUT pin to ground, nominal output capacitance must be greater than 0.47 uF; source page 3 |
| DC Output Accuracy | -2% min, +2% max; TJ = 25°C; source page 6 |
| Line Regulation | 20 mV typ, 50 mV max; VOUT(NOM) + 1 V <= VIN <= 24 V, TJ = 25°C; source page 6 |
| Load Regulation, VOUT < 3.3 V, 10 mA | 10 mV; 0 < IOUT < 10 mA, TJ = 25°C; source page 6 |
| Load Regulation, VOUT < 3.3 V, 50 mA | 25 mV; 0 < IOUT < 50 mA, TJ = 25°C; source page 6 |
| Load Regulation, VOUT < 3.3 V, 100 mA | 33 mV typ, 50 mV max; 0 < IOUT < 100 mA, TJ = 25°C; source page 6 |
| Load Regulation, VOUT >= 3.3 V, 10 mA | 7 mV; 0 < IOUT < 10 mA, TJ = 25°C; source page 6 |
| Load Regulation, VOUT >= 3.3 V, 50 mA | 35 mV; 0 < IOUT < 50 mA, TJ = 25°C; source page 6 |
| Load Regulation, VOUT >= 3.3 V, 100 mA | 50 mV typ, 75 mV max; 0 < IOUT < 100 mA, TJ = 25°C; source page 6 |
| Dropout Voltage, 10 mA | 75 mV; VIN = VOUT(nom) - 0.1 V, IOUT = 10 mA, TJ = 25°C; source page 6 |
| Dropout Voltage, 50 mA | 400 mV; VIN = VOUT(nom) - 0.1 V, IOUT = 50 mA, TJ = 25°C; source page 6 |
| Dropout Voltage, 100 mA | 850 mV typ, 1100 mV max; VIN = VOUT(nom) - 0.1 V, IOUT = 100 mA, TJ = 25°C; source page 6 |
| Output Current Limit, Legacy Chip | 160 mA min, 1000 mA max; VOUT = 0 V, TJ = 25°C; source page 6 |
| Output Current Limit, New Chip | 160 mA min, 500 mA max; VOUT = 0 V, TJ = 25°C; source page 6 |
| Power-Supply Ripple Rejection | 60 dB; f = 100 kHz, COUT = 10 uF; source page 6 |
| Operating Junction Temperature | -40°C to 125°C; recommended operating conditions and electrical characteristics; source page 5 |
| Absolute Maximum Junction Temperature | -40°C to 150°C; absolute maximum ratings; source page 4 |
| Storage Temperature | -65°C to 150°C; absolute maximum ratings; source page 4 |
| Absolute Maximum Input Voltage, Legacy Chip | -0.3 V to 24 V; legacy chip only; source page 4 |
| Absolute Maximum Input Voltage, New Chip | -0.3 V to 30 V; new chip only; source page 4 |
| Absolute Maximum Output Voltage, Legacy Chip | -0.3 V to 5.0 V; legacy chip only; source page 4 |
| Absolute Maximum Output Voltage, Fixed Output New Chip | -0.3 V to lower of 2 x VOUT(typ), VIN + 0.3 V, or 5.5 V; source page 4 |
| Peak Output Current | Internally limited; absolute maximum ratings; source page 4 |
| HBM ESD Rating | +/-2000 V; human body model per ANSI/ESDA/JEDEC JS-001, all pins; source page 4 |
| CDM ESD Rating | +/-500 V; charged device model per JEDEC JESD22-C101, all pins; source page 4 |
| Junction-to-Ambient Thermal Resistance, Legacy Chip | 213.1°C/W; DBV SOT-23 5-pin package; source page 5 |
| Junction-to-Ambient Thermal Resistance, New Chip | 170.8°C/W; DBV SOT-23 5-pin package; source page 5 |
| Junction-to-Case Top Thermal Resistance, Legacy Chip | 110.9°C/W; DBV SOT-23 5-pin package; source page 5 |
| Junction-to-Case Top Thermal Resistance, New Chip | 68.7°C/W; DBV SOT-23 5-pin package; source page 5 |
| Junction-to-Board Thermal Resistance, Legacy Chip | 97.4°C/W; DBV SOT-23 5-pin package; source page 5 |
| Junction-to-Board Thermal Resistance, New Chip | 76.7°C/W; DBV SOT-23 5-pin package; source page 5 |
| Junction-to-Top Characterization Parameter, Legacy Chip | 22.0°C/W; DBV SOT-23 5-pin package; source page 5 |
| Junction-to-Top Characterization Parameter, New Chip | 10.3°C/W; DBV SOT-23 5-pin package; source page 5 |
| Junction-to-Board Characterization Parameter, Legacy Chip | 78.4°C/W; DBV SOT-23 5-pin package; source page 5 |
| Junction-to-Board Characterization Parameter, New Chip | 76.3°C/W; DBV SOT-23 5-pin package; source page 5 |
| Datasheet Status | request_only |
Product Overview
The TLV704 is a Texas Instruments Power_Management IC identified as a low-dropout linear regulator. It is supplied in the DBV package, a 5-pin SOT-23 with 2.90 mm x 1.60 mm nominal body size, supporting compact regulated power rails where the specified 150 mA output capability is sufficient.
Recommended operation covers 2.5 V to 24 V at the input and 0 mA to 150 mA output current. Available fixed output options span 1.8 V to 5 V, while recommended output voltage operation is listed from 1.205 V to 5 V. Electrical output voltage range is specified from 1.2 V minimum to 5 V maximum at TJ = 25°C.
Capacitor selection is part of the operating constraints. The device requires at least 0.47 uF effective output capacitance for stability, with 1 uF nominal recommended for the new chip and 0.47 uF to 1 uF recommended for the legacy chip. An input capacitor of 0.047 uF effective is recommended to address source resistance and inductance, and 0.1 uF or larger is recommended from IN to ground.
Key Features
- Low-dropout linear regulator for Power_Management circuits
- 2.5 V to 24 V recommended input range
- New chip supports 30 V maximum input voltage
- Fixed output voltage options from 1.8 V to 5 V
- Recommended output current range from 0 mA to 150 mA
- 3.4 uA typical quiescent current at 100 mA load
- Requires at least 0.47 uF effective output capacitance
- 60 dB PSRR at 100 kHz with 10 uF COUT
- -2% to +2% DC output accuracy at TJ = 25°C
- DBV SOT-23 5-pin package, 2.90 mm x 1.60 mm
Typical Applications
- Low-current regulated power rails
- Compact Power_Management circuits
- Fixed-voltage board supplies
- 24 V input regulator stages
- 150 mA local rail regulation
- Temperature-rated embedded power rails
Procurement Notes
When requesting a quote for TLV704, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What input voltage range does the TLV704 support?
The TLV704 recommended input voltage range is 2.5 V to 24 V. For the new chip version, the feature summary lists a 30 V maximum input voltage, and the absolute maximum input voltage is -0.3 V to 30 V.
What output current is specified for the TLV704?
The recommended output current range is 0 mA to 150 mA. The feature summary also lists maximum output current as up to 150 mA, with output current limit specified separately for legacy and new chip versions.
What capacitors are required around the TLV704?
The output requires at least 0.47 uF effective capacitance for stability. The OUT pin recommendation is 1 uF or larger to ground. The IN pin recommendation is 0.1 uF or larger to ground, with 0.047 uF effective input capacitance recommended.
What package is used for the TLV704?
The TLV704 package case is DBV, described as a 5-pin SOT-23 package with a 2.90 mm x 1.60 mm nominal body size. Thermal resistance values are specified for this DBV SOT-23 5-pin package.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 20, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.