Specifications
| Type | Description |
|---|---|
| Part Number | TPS3813 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Component Type | Power_IC |
| Package / Case | DBV SOT-23 (6), 2.90 mm × 1.60 mm nominal body size |
| Function | Processor supervisory circuit with window-watchdog; condition: TPS3813xxx family |
| Supported Nominal Supply Monitor Voltages | 2.5 V, 3 V, 3.3 V, 5 V; condition: precision supply voltage monitor variants |
| Power-On Reset Delay Time | 25 ms typ; condition: fixed delay after VDD rises above threshold voltage VIT |
| Supply Current Feature Summary | 9 µA typ |
| Reset Output Type | Open-drain RESET output |
| Operating Temperature Range | -40°C to 85°C; condition: device characterization range |
| Threshold Voltage TPS3813J25DBV | 2.25 V |
| Threshold Voltage TPS3813L30DBV | 2.64 V |
| Threshold Voltage TPS3813K33DBV | 2.93 V |
| Threshold Voltage TPS3813I50DBV | 4.55 V |
| Pin 1 Function | WDI, watchdog timer input; must be driven at all times and not left floating |
| Pin 3 Function | WDT, programmable watchdog delay input; condition: DBV 6-pin SOT-23 package |
| Pin 5 Function | WDR, selectable watchdog window ratio input; must be tied to VDD or GND and not left floating |
| Absolute Maximum Supply Voltage | 6.5 V max; condition: over operating free-air temperature range |
| Absolute Maximum RESET Voltage | -0.3 V to VDD + 0.3 V; condition: with respect to GND |
| Absolute Maximum Voltage on Other Pins | -0.3 V to 6.5 V; condition: all pins except RESET and VDD |
| Maximum Low Output Current | 5 mA max; condition: absolute maximum rating, IOL |
| Maximum High Output Current | -5 mA max; condition: absolute maximum rating, IOH |
| Input Clamp Current | ±20 mA max; condition: VI < 0 V or VI > VDD |
| Output Clamp Current | ±20 mA max; condition: VO < 0 V or VO > VDD |
| Storage Temperature | -65°C to 150°C; condition: absolute maximum rating |
| ESD Rating HBM | ±2000 V; condition: human-body model per ANSI/ESDA/JEDEC JS-001 |
| ESD Rating CDM | ±750 V; condition: charged-device model per JEDEC JESD22-C101 |
| Recommended Supply Voltage | 2 V to 6 V; condition: specified temperature range |
| Recommended Input Voltage | 0 V to VDD + 0.3 V; condition: specified temperature range |
| High-Level Input Voltage | 0.7 × VDD min; condition: recommended operating condition |
| Low-Level Input Voltage | 0.3 × VDD max; condition: recommended operating condition |
| Input Transition Rise and Fall Rate | 100 ns/V max; condition: recommended operating condition |
| WDI Trigger Pulse Width | 50 ns min; condition: recommended operating condition |
| Junction-to-Ambient Thermal Resistance | 208.5°C/W; condition: DBV SOT-23, 6 pins |
| Low-Level Output Voltage at 500 µA | 0.2 V max; condition: VDD = 2 V to 6 V, IOL = 500 µA |
| Low-Level Output Voltage at 2 mA | 0.4 V max; condition: VDD = 3.3 V, IOL = 2 mA |
| Power-Up Reset Voltage | 0.2 V max; condition: VDD ≥ 1.1 V, IOL = 50 µA |
| Negative-Going Input Threshold Voltage TPS3813J25 | 2.2 V min, 2.25 V typ, 2.3 V max; condition: TA = -40°C to +85°C |
| Negative-Going Input Threshold Voltage TPS3813L30 | 2.58 V min, 2.64 V typ, 2.7 V max; condition: TA = -40°C to +85°C |
| Negative-Going Input Threshold Voltage TPS3813K33 | 2.87 V min, 2.93 V typ, 3.0 V max; condition: TA = -40°C to +85°C |
| Negative-Going Input Threshold Voltage TPS3813I50 | 4.45 V min, 4.55 V typ, 4.65 V max; condition: TA = -40°C to +85°C |
| Threshold Hysteresis TPS3813J25 | 30 mV typ |
| Threshold Hysteresis TPS3813L30 | 35 mV typ |
| Threshold Hysteresis TPS3813K33 | 40 mV typ |
| Threshold Hysteresis TPS3813I50 | 60 mV typ |
| Supply Current at 2 V | 9 µA typ, 13 µA max; condition: VDD = 2 V, output unconnected |
| Supply Current at 5 V | 20 µA typ, 25 µA max; condition: VDD = 5 V, output unconnected |
| Input Capacitance | 5 pF typ; condition: VI = 0 V to VDD |
| VIT Glitch Immunity | 3 µs typ; condition: VDD = VIT + 0.2 V to VDD = VIT - 0.2 V, RL = 1 MΩ, CL = 50 pF, TA = -40°C to +85°C |
| Reset Delay Time | 20 ms min, 25 ms typ, 30 ms max; condition: VDD ≥ VIT + 0.2 V |
| Watchdog Time-Out Upper Limit, WDT = 0 V | 0.2 s min, 0.25 s typ, 0.3 s max |
| Watchdog Time-Out Upper Limit, WDT = VDD | 2 s min, 2.5 s typ, 3 s max |
| Programmable Watchdog Time-Out Formula | (Cext ÷ 15.55 pF + 1) × 6.25 ms; condition: WDT programmable, 155 pF < Cext < 63 nF |
| Watchdog Window Ratio, WDR = 0 V | 1:31.8; condition: WDR = 0 V, WDT = 0 V |
| Watchdog Window Ratio, WDR = VDD | 1:127.7; condition: WDR = VDD, WDT = VDD |
| VDD to RESET Propagation Delay | 30 µs typ, 50 µs max; condition: high-to-low output, VIL = VIT - 0.2 V, VIH = VIT + 0.2 V |
| Power Dissipation Rating | 437 mW; condition: DBV package, TA < 25°C |
| Power Derating Factor | 3.5 mW/°C; condition: DBV package, above TA = 25°C |
| Datasheet Status | request_only |
Product Overview
The TPS3813 is a Texas Instruments processor supervisory circuit for Power_Management designs that require supply monitoring and a window-watchdog input. The TPS3813xxx family provides precision monitor variants for nominal 2.5 V, 3 V, 3.3 V, and 5 V supplies, with negative-going threshold options specified for TPS3813J25, TPS3813L30, TPS3813K33, and TPS3813I50 devices.
The RESET output is open-drain, with low-level output ratings of 0.2 V maximum at 500 µA and 0.4 V maximum at 2 mA under the stated supply conditions. Reset timing includes a 20 ms to 30 ms reset delay range, with 25 ms typical after VDD exceeds the threshold. The device also specifies 30 µs typical VDD-to-RESET propagation delay for high-to-low output transitions.
The DBV SOT-23 6-pin package has a 2.90 mm × 1.60 mm nominal body size and 208.5°C/W junction-to-ambient thermal resistance. WDI must be driven at all times, WDR must be tied to VDD or GND, and WDT supports fixed or externally programmed watchdog timing.
Key Features
- Processor supervisory circuit with window-watchdog function
- Monitors 2.5 V, 3 V, 3.3 V, and 5 V supplies
- 25 ms typical power-on reset delay after VDD threshold crossing
- Open-drain RESET output for monitored reset signaling
- 2 V to 6 V recommended supply voltage range
- WDT pin supports programmable watchdog delay input
- Selectable watchdog window ratio through WDR input
- 50 ns minimum WDI trigger pulse width
- -40°C to 85°C characterized operating temperature range
- DBV SOT-23 6-pin package with 208.5°C/W thermal resistance
Typical Applications
- Processor supply supervision
- Window-watchdog monitoring
- Power-on reset generation
- 2.5 V rail monitoring
- 3 V rail monitoring
- 3.3 V rail monitoring
- 5 V rail monitoring
- Compact SOT-23 power management
Procurement Notes
When requesting a quote for TPS3813, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What type of device is the TPS3813?
The TPS3813 is a Texas Instruments processor supervisory circuit in the Power_Management category. The TPS3813xxx family includes a window-watchdog function and precision supply voltage monitor variants for 2.5 V, 3 V, 3.3 V, and 5 V nominal rails.
What package is specified for TPS3813 devices?
The extracted package information identifies the TPS3813 in a DBV SOT-23 6-pin package. The nominal package body size is 2.90 mm × 1.60 mm, and the listed junction-to-ambient thermal resistance is 208.5°C/W.
What reset timing does the TPS3813 provide?
The TPS3813 has a fixed power-on reset delay of 25 ms typical after VDD rises above the threshold voltage. The reset delay time is specified as 20 ms minimum, 25 ms typical, and 30 ms maximum when VDD is at least VIT + 0.2 V.
How should the watchdog pins be handled?
Pin 1 is WDI and must be driven at all times, not left floating. Pin 3 is WDT for programmable watchdog delay input. Pin 5 is WDR for selectable watchdog window ratio and must be tied to VDD or GND.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 8, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.