Specifications
| Type | Description |
|---|---|
| Part Number | TPS54J060 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Package Case | RPG (VQFN-HR, 14), 3 mm x 2 mm, 0.5 mm pitch |
| Input voltage range with external bias | 2.7 to 16 V; External bias on VCC up to 3.6 V |
| Input voltage range without external bias | 4 to 16 V; Internal bias operation |
| Continuous output current | 6 A; Integrated MOSFETs |
| Output voltage range | 0.9 to 5.5 V; Regulated output range |
| Reference voltage | 900 mV ±1%; TJ = -40°C to +125°C |
| Control mode | D-CAP3 adaptive on-time control; Synchronous buck converter operation |
| Selectable switching frequencies | 600 kHz, 1100 kHz, 2200 kHz; Selected by MODE pin |
| Fault response | Latch-off for OC, UV, and OV faults; Overcurrent, undervoltage, and overvoltage faults |
| Maximum VIN pin voltage | -0.3 to 18 V; Absolute maximum rating, with respect to ground |
| Maximum BOOT-SW voltage | -0.3 to 6 V; Absolute maximum rating |
| Maximum EN and PGOOD pin voltage | -0.3 to 6 V; Absolute maximum rating |
| Operating junction temperature absolute range | -40 to 150 °C; Absolute maximum rating |
| Recommended operating junction temperature | -40 to 125 °C; Recommended operating conditions |
| HBM ESD rating | ±2000 V; ANSI/ESDA/JEDEC JS-001 |
| CDM ESD rating | ±500 V; ANSI/ESDA/JEDEC JS-002 |
| Recommended VCC voltage | 3.0 to 3.6 V; Recommended operating conditions |
| Junction-to-ambient thermal resistance | 64 °C/W; RθJA, JEDEC, RPG 14-pin QFN package |
| Junction-to-case top thermal resistance | 40 °C/W; RθJC(top), JEDEC, RPG 14-pin QFN package |
| Junction-to-case bottom thermal resistance | 16.2 °C/W; RθJC(bot), JEDEC, RPG 14-pin QFN package |
| VIN operating non-switching supply current | 750 typ, 900 max µA; VEN = 2 V, VFB = VINTREF + 50 mV, VIN = 12 V, no external bias on VCC |
| External VCC bias current at 600 kHz | 3 mA; 3.3 V external bias on VCC pin, fSW(FCCM) = 600 kHz |
| External VCC bias current at 1100 kHz | 5.5 mA; 3.3 V external bias on VCC pin, fSW(FCCM) = 1100 kHz |
| External VCC bias current at 2200 kHz | 10 mA; 3.3 V external bias on VCC pin, fSW(FCCM) = 2200 kHz |
| VIN shutdown supply current | 10 µA; VEN = 0 V, VIN = 12 V, no external bias on VCC pin |
| VIN UVLO rising threshold | 2.1 min, 2.4 typ, 2.7 max V; VIN rising, VCC = external 3.3 V bias |
| VIN UVLO falling threshold | 1.55 min, 1.85 typ, 2.15 max V; VIN falling, VCC = external 3.3 V bias |
| EN enable threshold voltage | 1.17 min, 1.22 typ, 1.27 max V; VENH, rising |
| EN disable threshold voltage | 0.97 min, 1.02 typ, 1.07 max V; VENL, falling |
| EN hysteresis voltage | 0.2 V; VENHYST |
| EN input leakage current | -5 min, 0 typ, 5 max µA; VEN = 3.3 V |
| EN internal pull-down resistance | 6500 kΩ; EN pin to AGND |
| Internal LDO output voltage | 2.90 min, 3.00 typ, 3.10 max V; VIN = 12 V, IVCC(LOAD) = 5 mA |
| VCC UVLO rising threshold | 2.80 min, 2.85 typ, 2.90 max V; VCC rising |
| VCC UVLO falling threshold | 2.65 min, 2.70 typ, 2.75 max V; VCC falling |
| LDO dropout voltage | 310 mV; VIN = 3.3 V, IVCC(LOAD) = 20 mA, TJ = 25°C |
| LDO overcurrent limit | 30 min, 60 typ mA; All VINs, all temperatures |
| Internal reference voltage | 900 mV; TJ = 25°C |
| Internal reference voltage tolerance | 896 min, 904 max mV; TJ = 0°C to 70°C |
| Internal reference voltage tolerance | 891 min, 909 max mV; TJ = -40°C to 125°C |
| FB input current | 100 nA; VFB = VINTREF |
| Switching frequency | 935 min, 1100 typ, 1265 max kHz; FCCM, VIN = 12 V, VOUT = 1.2 V, RMODE = 0 Ω to AGND, no load |
| Switching frequency | 1870 min, 2200 typ, 2530 max kHz; FCCM, VIN = 12 V, VOUT = 2.5 V, RMODE = 30.1 kΩ to AGND, no load |
| Switching frequency | 536 min, 630 typ, 724 max kHz; FCCM, VIN = 12 V, VOUT = 1.2 V, RMODE = 60.4 kΩ to AGND, no load |
| Minimum on-time | 70 typ, 95 max ns; VIN = 12 V, VOUT = 1 V, first pulse |
| Minimum off-time | 220 ns; TJ = 25°C, high-side FET gate falling to rising |
| EN to first switching delay with internal LDO | 0.85 typ, 2 max ms; Internal 3.0 V LDO, VCC bypass cap = 1 µF typical or 2.2 µF max, CSS/REFIN = 1 nF |
| EN to first switching delay with external VCC bias | 500 typ, 700 max µs; External 3.3 V VCC bias, CSS/REFIN = 1 nF |
| Internal soft-start time | 1 typ, 1.5 max ms; REFIN rising from 0 V to 95% of final setpoint, CSS/REFIN = 1 nF |
| SS/REFIN sourcing current | 9 µA; VSS/REFIN = 0 V |
| SS/REFIN sinking current | 3 µA; VSS/REFIN = 1 V |
| SSREFIN detection threshold | 550 mV; VIN = 4 V to 16 V, VCC = 3.0 V to 5.3 V, -40°C to 125°C |
| SS/REFIN to FB matching | -5 min, 0 typ, 5 max mV; VSS/REFIN = 0.5 V |
| High-side MOSFET on-resistance | 22 mΩ; TJ = 25°C, BOOT-SW = 3 V, IO = 3 A |
| Low-side MOSFET on-resistance | 8.5 mΩ; TJ = 25°C, VCC = 3 V, IO = 3 A |
| VBST-SW leakage current | 28 µA; TJ = 25°C, VVBST-SW = 3.3 V |
| BOOT UVLO rising threshold | 2.35 V; TJ = 25°C, voltage rising |
| BOOT UVLO hysteresis | 0.32 V; TJ = 25°C |
| Current limit clamp | 8.1 min, 9.5 typ A; Valley current on low-side FET, 0 Ω ≤ RTRIP ≤ 3.16 kΩ |
| TRIP pin resistance range | 3.74 to 30.1 kΩ; RTRIP |
| Current limit threshold | 5.1 min, 6.0 typ, 6.9 max A; Valley current on low-side FET, RTRIP = 4.99 kΩ |
| Negative current limit threshold | -4.3 min, -3.5 typ, -2.8 max A; All VINs |
| Zero-cross detection current threshold | 0 min, 200 typ, 730 max mA; Open loop, VIN = 12 V, VCC = 3 V |
| Overvoltage protection threshold | 113 min, 116 typ, 119 max %; VOVP |
| Undervoltage protection threshold | 77 min, 80 typ, 83 max %; VUVP |
| OVP response delay | 300 ns; With 100 mV overdrive |
| UVP filter delay | 64 µs; Undervoltage protection |
| PGOOD rising threshold | 89 min, 92.5 typ, 95 max %; FB rising, PGOOD transition low to high |
| PGOOD high-to-low overvoltage threshold | 113 min, 116 typ, 119 max %; FB rising, PGOOD transition high to low |
| PGOOD falling threshold | 77 min, 80 typ, 83 max %; FB falling, PGOOD transition high to low |
| PGOOD out-of-bounds threshold | 102.5 min, 105 typ, 107.5 max %; FB rising |
| PGOOD sink current | 5.5 mA; VPGOOD = 0.4 V, VIN = 12 V, VCC = 3 V |
| Datasheet Status | request_only |
Product Overview
Control is based on D-CAP3 adaptive on-time operation, with switching frequency selected by the MODE pin at 600 kHz, 1100 kHz, or 2200 kHz. The internal reference is 900 mV, with a ±1% reference specification across -40°C to +125°C junction temperature. Protection behavior includes latch-off response for overcurrent, undervoltage, and overvoltage faults.
Key Features
- 6 A continuous output current with integrated MOSFETs
- 2.7 V to 16 V input with external VCC bias
- 4 V to 16 V input with internal bias operation
- 0.9 V to 5.5 V regulated output range
- D-CAP3 adaptive on-time synchronous buck control
- MODE pin selects 600 kHz, 1100 kHz, or 2200 kHz
- Latch-off response for overcurrent, undervoltage, and overvoltage faults
- 900 mV reference specified to ±1% over temperature
- RPG VQFN-HR 14 package, 3 mm x 2 mm
- PGOOD thresholds monitor feedback undervoltage and overvoltage conditions
Typical Applications
- 6 A regulated point-of-load rails
- Externally biased step-down rails
- Internally biased buck regulation
- PGOOD-monitored supply rails
- Selectable-frequency power stages
- Soft-start controlled supplies
- Compact 3 mm x 2 mm power designs
Procurement Notes
When requesting a quote for TPS54J060, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What input voltage range does TPS54J060 support?
TPS54J060 supports 2.7 V to 16 V input when using external VCC bias up to 3.6 V. For internal bias operation, the specified input voltage range is 4 V to 16 V.
What output current and voltage range are specified?
The device provides 6 A continuous output current with integrated MOSFETs. Its regulated output voltage range is 0.9 V to 5.5 V, using a 900 mV internal reference.
Which switching frequencies can be selected?
The TPS54J060 uses D-CAP3 adaptive on-time control and provides selectable switching frequencies through the MODE pin. The listed selections are 600 kHz, 1100 kHz, and 2200 kHz.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 20, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.