Specifications
| Type | Description |
|---|---|
| Part Number | TPS56221 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Component Type | Power_IC |
| Package Case | 22-pin PQFN PowerPAD / LSON-CLIP, 6.00 mm x 5.00 mm body |
| Input Voltage Range | 4.5 to 14 V; recommended operating condition, VIN/VDD input |
| Output Current | up to 25 A; device capability stated in features/description |
| Minimum Output Voltage | as low as 0.6 V; regulated output capability |
| Feedback Reference Voltage | 597 / 600 / 603 mV min/typ/max; TJ=25°C, 4.5 V <= VDD <= 14 V |
| Feedback Reference Voltage | 594 / 600 / 606 mV min/typ/max; -40°C <= TJ <= 125°C, 4.5 V <= VDD <= 14 V |
| Reference Accuracy | 1%; 600 mV reference voltage |
| Shutdown Supply Current | 80 / 120 µA typ/max; VEN/SS = 0.2 V |
| Quiescent Non-Switching Current | 2.5 / 5.0 mA typ/max; EN/SS floating, VFB = 1 V |
| UVLO On Voltage | 4.0 / 4.3 V typ/max; input supply undervoltage lockout |
| UVLO Hysteresis | 500 / 700 mV typ/max; input supply undervoltage lockout hysteresis |
| EN/SS High-Level Input Voltage | 0.55 / 0.70 / 1.00 V min/typ/max; enable/soft-start input |
| EN/SS Low-Level Input Voltage | 0.27 / 0.30 / 0.33 V min/typ/max; enable/soft-start input |
| Soft-Start Source Current | 8 / 10 / 12 µA min/typ/max; EN/SS soft-start current source |
| Soft-Start Start-of-Ramp Voltage | 0.4 / 0.8 / 1.3 V min/typ/max; soft-start voltage level at start of ramp |
| BP Regulator Output Voltage | 6.2 / 6.5 / 6.8 V min/typ/max; IBP = 10 mA |
| BP Regulator Dropout Voltage | 70 / 125 mV typ/max; IBP = 25 mA, VDD = 4.5 V |
| Switching Frequency | 270 / 300 / 330 kHz min/typ/max; RCOMP = 40.2 kΩ, 4.5 V <= VDD <= 14 V |
| Switching Frequency | 450 / 500 / 550 kHz min/typ/max; RCOMP open, 4.5 V <= VDD <= 14 V |
| Switching Frequency | 0.8 / 0.95 / 1.1 MHz min/typ/max; RCOMP = 13.3 kΩ, 4.5 V <= VDD <= 14 V |
| Ramp Amplitude | VDD/6.6 / VDD/6 / VDD/5.4 min/typ/max; PWM ramp amplitude, ensured by design |
| Maximum Duty Cycle | 93%; fsw = 300 kHz, VFB = 0 V, 4.5 V <= VDD <= 14 V |
| Maximum Duty Cycle | 90%; fsw = 500 kHz, VFB = 0 V, 4.5 V <= VDD <= 14 V |
| Maximum Duty Cycle | 85%; fsw = 1 MHz, VFB = 0 V, 4.5 V <= VDD <= 14 V |
| Minimum Controllable Pulse Width | 100 ns; PWM operation, ensured by design |
| Error Amplifier Gain Bandwidth Product | 10 / 24 MHz min/typ; ensured by design |
| Error Amplifier Open Loop Gain | 60 dB; ensured by design |
| Feedback Input Bias Current | 75 nA; current out of FB pin, VFB = 0.6 V |
| Error Amplifier Output Source Current | 1.5 mA; VFB = 0 V |
| Error Amplifier Output Sink Current | 1.5 mA; VFB = 1 V |
| Power Good Feedback Upper Voltage Limit | 655 / 675 / 700 mV min/typ/max; PGOOD upper threshold |
| Power Good Feedback Lower Voltage Limit | 500 / 525 / 550 mV min/typ/max; PGOOD lower threshold |
| Power Good Hysteresis at FB | 30 / 45 mV typ/max; PGOOD hysteresis voltage at FB |
| Power Good Pulldown Resistance | 30 / 70 Ω typ/max; VFB = 0 V, IFB = 5 mA |
| Power Good Leakage Current | 10 / 20 µA typ/max; 550 mV < VFB < 655 mV, VPGOOD = 5 V |
| High-Side MOSFET On Resistance | 4.5 / 6.5 mΩ typ/max; TJ = 25°C, VBOOT - VSW = 5.5 V |
| Low-Side MOSFET On Resistance | 1.9 / 2.7 mΩ typ/max; TJ = 25°C |
| Minimum Pulse Time During Short Circuit | 250 ns; overcurrent protection, ensured by design |
| Switch Leading-Edge Blanking Pulse Time | 150 ns; high-side detection, ensured by design |
| High-Side FET Overcurrent Threshold | 45 / 54 / 65 A min/typ/max; TJ = 25°C, VBOOT - VSW = 5.5 V |
| Operating Junction Temperature | -40 to 125°C; recommended operating condition |
| Absolute Maximum VDD/VIN Voltage | -0.3 to 16.5 V; over operating free-air temperature range |
| Absolute Maximum SW Voltage | -3 to 25 V; over operating free-air temperature range |
| Absolute Maximum SW Transient Voltage | -5 V; pulse width <100 ns, 10 µJ |
| Absolute Maximum BOOT Voltage | -0.3 to 30 V; over operating free-air temperature range |
| Absolute Maximum BOOT-SW Differential Voltage | -0.3 to 7 V; differential from BOOT to SW |
| Absolute Maximum Signal Pin Voltage | -0.3 to 7 V; COMP, PGOOD, FB, BP, EN/SS, ILIM pins |
| Absolute Maximum Junction Temperature | -40 to 150°C; absolute maximum rating |
| Storage Temperature | -55 to 150°C; absolute maximum rating |
| ESD Rating HBM | ±2000 V; human body model, ANSI/ESDA/JEDEC JS-001 |
| ESD Rating CDM | ±1500 V; charged-device model, JEDEC JESD22-C101 |
| Junction-to-Ambient Thermal Resistance | 34.6°C/W; PQFN 22-pin package |
| Junction-to-Case Top Thermal Resistance | 22.9°C/W; PQFN 22-pin package |
| Junction-to-Top Characterization Parameter | 0.6°C/W; PQFN 22-pin package |
| Junction-to-Board Characterization Parameter | 5.0°C/W; PQFN 22-pin package |
| Junction-to-Case Bottom Thermal Resistance | 0.3°C/W; PQFN 22-pin package |
| BOOT Capacitor Recommendation | 100 nF typical; connect between BOOT and SW pins |
| BOOT Series Resistor Recommendation | 5 to 10 Ω; optional resistor in series with BOOT capacitor to reduce SW voltage spike |
| BP Bypass Capacitor Recommendation | 1 µF or greater; low-ESR ceramic capacitor from BP to GND |
| VDD Bypass Capacitor Recommendation | 1 µF; low-ESR ceramic capacitor from VDD close to GND |
| Frequency Programming Resistor for 300 kHz | 40.2 kΩ; resistor from COMP to GND sets switching frequency to 300 kHz |
| Frequency Programming Resistor for 1 MHz | 13.3 kΩ; resistor from COMP to GND sets switching frequency to 1 MHz |
| Default Switching Frequency | 500 kHz; COMP resistor open |
| Soft-Start Programming Current | 10 µA; internal current source charges capacitor connected from EN/SS to GND |
| Soft-Start Ramp Final Voltage | 1.4 V typical; EN/SS voltage ramp reaches this level |
| Control Method | Voltage-mode control with feed-forward; device control architecture |
| Prebiased Output Support | Supported; feature list |
| Thermal Shutdown | Supported; feature list |
| Power Good Output Type | Open-drain; PGD pin function |
| Overcurrent Limit Programming | External resistor from ILIM to GND; programs low-side FET overcurrent threshold |
| Datasheet Status | request_only |
Product Overview
The TPS56221 is a Texas Instruments synchronous buck converter for Power_Management designs requiring a 4.5 to 14 V VIN/VDD input and output current capability up to 25 A. It regulates outputs as low as 0.6 V and uses voltage-mode control with feed-forward. The feedback reference is 600 mV typical, with 1% reference accuracy specified for the 600 mV reference voltage.
Frequency configuration is supported through the COMP pin: 40.2 kΩ sets 300 kHz, an open COMP resistor selects the 500 kHz default, and 13.3 kΩ sets 1 MHz. The device includes programmable soft start using a capacitor from EN/SS to GND charged by a 10 µA internal current source, with a typical 1.4 V ramp final voltage.
The package is a 22-pin PQFN PowerPAD / LSON-CLIP with a 6.00 mm x 5.00 mm body. Layout-related component guidance includes a 100 nF BOOT capacitor between BOOT and SW, optional 5 to 10 Ω BOOT series resistance to reduce SW voltage spike, at least 1 µF BP bypass capacitance, and a 1 µF VDD bypass capacitor placed close to GND.
Key Features
- 4.5 to 14 V VIN/VDD recommended input range
- Output current capability up to 25 A
- Regulated output voltage as low as 0.6 V
- 600 mV feedback reference with 1% accuracy
- Selectable 300 kHz, 500 kHz, or 1 MHz switching
- Voltage-mode control with feed-forward architecture
- Open-drain power-good output with FB thresholds
- External ILIM resistor programs low-side overcurrent threshold
- Prebiased output startup support
- Thermal shutdown support
Typical Applications
- High-current point-of-load regulation
- Low-voltage buck power rails
- 4.5 to 14 V input systems
- 25 A synchronous step-down supplies
- Prebiased output power sequencing
- Power rails needing power-good monitoring
Procurement Notes
When requesting a quote for TPS56221, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What input voltage range does TPS56221 support?
TPS56221 is specified for a recommended VIN/VDD input operating range of 4.5 to 14 V. Absolute maximum VDD/VIN voltage is listed separately as -0.3 to 16.5 V.
What output current and voltage range are stated for TPS56221?
The device capability is stated as output current up to 25 A. Its regulated output capability is specified as output voltage as low as 0.6 V.
How is TPS56221 switching frequency configured?
Switching frequency is set at 300 kHz with 40.2 kΩ from COMP to GND, defaults to 500 kHz with the COMP resistor open, and is set to 1 MHz with 13.3 kΩ.
What package is used for TPS56221?
TPS56221 is provided in a 22-pin PQFN PowerPAD / LSON-CLIP package with a 6.00 mm x 5.00 mm body. Thermal data includes 34.6°C/W junction-to-ambient resistance.
What external capacitors are recommended around TPS56221?
The extracted facts specify a typical 100 nF BOOT capacitor between BOOT and SW, a BP bypass capacitor of 1 µF or greater from BP to GND, and a 1 µF VDD bypass capacitor close to GND.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 20, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.