Specifications
| Type | Description |
|---|---|
| Part Number | TPS62303 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Package / Case | QFN-10 3 x 3 mm; CSP-8 chip-scale package (NanoFree/NanoStar) |
| Output voltage | 1.8 V; TPS62303 fixed-output version |
| Output current | Up to 500 mA; VI = 2.7 V |
| Input voltage range | 2.7 to 6 V; operating range |
| Switching frequency | 3 MHz fixed; normal operation |
| Oscillator frequency | 2.65 min, 3 typ, 3.35 max MHz; VI = 3.6 V, VO = 1.6 V, EN = VI, MODE/SYNC = GND, L = 1 uH, CO = 10 uF, TA = -40 to 85 C |
| Synchronization range | 2.65 to 3.35 MHz; external clock synchronization |
| External clock duty cycle | 20% min, 80% max; synchronization clock signal |
| Efficiency | Up to 93%; 3-MHz operation |
| Quiescent current | 86 typ, 105 max uA; TPS6230x/TPS6232x, IO = 0 mA, PFM enabled, device not switching |
| No-load switching current | 3.6 mA typ; TPS6230x/TPS6231x/TPS6232x, IO = 0 mA, MODE/SYNC = VIN |
| Shutdown current | 0.1 typ, 1 max uA; EN = GND |
| Undervoltage lockout threshold | 2.40 typ, 2.55 max V; TPS6230x/TPS6232x |
| EN high-level input voltage | 1.2 V min; enable input high |
| MODE/SYNC high-level input voltage | 1.3 V min; MODE/SYNC input high |
| EN low-level input voltage | 0.4 V max; enable input low |
| MODE/SYNC low-level input voltage | 0.4 V max; MODE/SYNC input low |
| EN input leakage current | 0.01 typ, 1 max uA; EN = GND or VIN |
| MODE/SYNC input leakage current | 0.01 typ, 1 max uA; MODE/SYNC = GND or VIN |
| P-channel MOSFET on-resistance | 420 typ, 750 max mohm; TPS6230x, VI = VGS = 3.6 V |
| P-channel MOSFET leakage current | 1 uA max; VDS = 6 V |
| N-channel MOSFET on-resistance | 330 typ, 750 max mohm; VI = VGS = 3.6 V |
| N-channel MOSFET on-resistance | 400 typ, 1000 max mohm; VI = VGS = 2.8 V |
| N-channel MOSFET leakage current | 1 uA max; VDS = 6 V |
| P-MOS current limit | 670 min, 780 typ, 890 max mA; 2.7 V <= VI <= 6 V |
| N-MOS current limit sourcing | 550 min, 720 typ, 890 max mA; 2.7 V <= VI <= 6 V |
| N-MOS current limit sinking | -460 min, -600 typ, -740 max mA; 2.7 V <= VI <= 6 V |
| Input current limit under short circuit | 390 mA typ; VO = 0 V |
| Thermal shutdown | 150 C typ; junction temperature protection |
| Thermal shutdown hysteresis | 20 C typ; after thermal shutdown |
| Fixed output voltage accuracy | -2% min, +2% max; TPS6230x/TPS62311/TPS62313/TPS6232x, 2.7 V <= VI <= 6 V, 0 mA <= IO(DC) <= 500 mA, PFM/PWM mode operation |
| Fixed output voltage DC accuracy | -0.5% min, +1.3% max; TPS6230x, TA = 25 C, PWM mode operation, VI = 3.6 V, no load |
| Fixed output voltage DC accuracy | -0.5% min, +1.3% max; TPS6230x/TPS62311/TPS62313/TPS6232x, -40 C <= TA <= 85 C, PWM mode operation, VI = 3.6 V, no load |
| DC output voltage load regulation | -0.001 typ, -0.002 max %/mA; IO = 0 mA to 500 mA, MODE/SYNC = VI |
| DC output voltage line regulation | 0.11 typ, 0.2 max %/V; VI = VO + 0.5 V, minimum 2.7 V, to 6 V; IO = 100 mA; MODE/SYNC = VI |
| Power-save mode ripple voltage | 0.025 VO Vp-p typ; IO = 1 mA, MODE/SYNC = GND |
| Start-up time | 250 us typ; IO = 200 mA, time from active EN to VO |
| Minimum on-time | 35 ns typ; P-channel MOSFET |
| Resistance into VOUT sense pin | 700 typ, 1000 max kohm; VOUT sense input |
| Leakage current into SW pin | 0.1 typ, 1 max uA; VI > VO, 0 V <= VSW <= VIN, EN = GND |
| Reverse leakage current into SW pin | 0.1 typ, 1 max uA; VI = open, VSW = 6 V, EN = GND |
| Operating ambient temperature range | -40 to 85 C; recommended/orderable operating temperature range |
| Maximum operating junction temperature | 150 C; absolute maximum rating |
| Storage temperature range | -65 to 150 C; absolute maximum rating |
| VIN/AVIN absolute maximum voltage | -0.3 to 7 V; voltage with respect to ground |
| SW absolute maximum voltage | -0.3 to 7 V; voltage with respect to ground |
| EN/MODE-SYNC absolute maximum voltage | -0.3 to VI + 0.3 V; voltage with respect to ground |
| VOUT absolute maximum voltage | 0.3 to 5.4 V; voltage with respect to ground |
| Continuous output current absolute maximum | 500 mA; absolute maximum rating |
| ESD rating | 2 kV; human body model at AVIN, FB, ADJ, EN, MODE_SYNC, VOUT |
| ESD rating | 1 kV; human body model at VIN, SW |
| ESD rating | 1.5 kV; charged device model |
| QFN thermal resistance | 49 C/W; DRC package, low-K board per JESD51-7 |
| QFN power rating | 2050 mW; DRC package, TA <= 25 C |
| QFN derating factor | 21 mW/C; DRC package, above TA = 25 C |
| CSP thermal resistance | 250 C/W; YZD package, low-K board per JESD51-7 |
| CSP power rating | 400 mW; YZD package, TA <= 25 C |
| Datasheet Status | request_only |
Product Overview
Control and operating data include PFM-enabled no-switching quiescent current of 86 uA typical and 105 uA maximum, shutdown current of 0.1 uA typical and 1 uA maximum when EN is low, and no-load switching current of 3.6 mA typical when MODE/SYNC is tied to VIN. External synchronization is supported from 2.65 to 3.35 MHz with a 20% to 80% clock duty-cycle range.
The device includes current-limit and protection specifications, including P-MOS current limit from 670 to 890 mA, N-MOS sourcing current limit from 550 to 890 mA, N-MOS sinking current limit from -460 to -740 mA, undervoltage lockout at 2.40 V typical and 2.55 V maximum, and 150 C typical thermal shutdown with 20 C typical hysteresis.
Package options include QFN-10 3 x 3 mm and CSP-8 NanoFree/NanoStar chip-scale packages. The QFN DRC package is specified at 49 C/W thermal resistance and 2050 mW power rating at TA <= 25 C, while the CSP YZD package is specified at 250 C/W and 400 mW under the same board and temperature condition.
Key Features
- 1.8 V fixed-output version for regulated rails
- Up to 500 mA output current at VI = 2.7 V
- 2.7 to 6 V operating input voltage range
- 3 MHz fixed switching frequency in normal operation
- External synchronization from 2.65 to 3.35 MHz
- Up to 93% efficiency during 3-MHz operation
- 86 uA typical quiescent current with PFM enabled
- 0.1 uA typical shutdown current when EN is low
- 250 us typical start-up time at 200 mA load
- 150 C typical thermal shutdown with 20 C hysteresis
Typical Applications
- 1.8 V regulated power rails
- 500 mA point-of-load conversion
- 2.7 to 6 V input systems
- Externally synchronized power designs
- PFM-enabled light-load regulation
- Compact QFN power assemblies
- CSP chip-scale power layouts
Procurement Notes
When requesting a quote for TPS62303, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What output voltage does TPS62303 provide?
The TPS62303 fixed-output version provides a 1.8 V output. The extracted datasheet facts identify it as a synchronous step-down converter with output current support up to 500 mA at VI = 2.7 V.
What input voltage range does TPS62303 support?
TPS62303 operates across a 2.7 to 6 V input voltage range. Absolute maximum ratings list VIN/AVIN and SW from -0.3 to 7 V with respect to ground.
What switching and synchronization frequencies are specified?
Normal operation uses a 3 MHz fixed switching frequency. The oscillator frequency is specified from 2.65 MHz minimum to 3.35 MHz maximum, and external clock synchronization supports the same 2.65 to 3.35 MHz range.
Which package options are listed for TPS62303?
The package information lists QFN-10 3 x 3 mm and CSP-8 chip-scale package options, including NanoFree and NanoStar naming. Thermal data is provided separately for DRC QFN and YZD CSP packages.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 25, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.