Specifications
| Type | Description |
|---|---|
| Part Number | TPS7A10 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Package / Case | WSON-6 1.50 mm x 1.50 mm; DSBGA-5 0.74 mm x 1.09 mm, 0.35-mm pitch |
| Component Type | Power_IC |
| Output Current | 300 mA; Maximum sourced load current |
| Input Voltage Range | 0.75 to 3.3 V; Recommended operating condition |
| Bias Voltage Range | 1.7 to 5.5 V; Recommended operating condition |
| Output Voltage Range | 0.5 to 3.0 V; Fixed-output voltages in 50-mV steps |
| Output Accuracy | ±1.5 %; -40°C ≤ TJ ≤ 125°C, VOUT(NOM)+0.5 V ≤ VIN ≤ 3.3 V, VOUT(NOM)+1.4 V ≤ VBIAS ≤ 5.5 V, 1 mA ≤ IOUT ≤ 300 mA |
| Nominal Accuracy | ±0.5 %; TJ = 25°C |
| Output Accuracy | ±1.25 %; -20°C ≤ TJ ≤ 85°C, DSE package, 1 mA ≤ IOUT ≤ 300 mA |
| Output Accuracy | ±1.25 %; -40°C ≤ TJ ≤ 85°C, YKA package, 1 mA ≤ IOUT ≤ 300 mA |
| VIN Line Regulation | 0.001 %/V; VOUT(NOM)+0.5 V ≤ VIN ≤ 3.3 V |
| VBIAS Line Regulation | 0.03 %/V; VOUT(NOM)+1.4 V ≤ VBIAS ≤ 5.5 V |
| Load Regulation | 0.2 %/A; 0.1 mA ≤ IOUT ≤ 300 mA |
| Bias Pin Quiescent Current | 3 µA typ, 6 µA min, 8 µA max; TJ = 25°C, IOUT = 0 mA |
| Bias Pin Quiescent Current | 11 µA max; -40°C < TJ < 85°C, IOUT = 0 mA |
| Bias Pin Quiescent Current | 14 µA max; IOUT = 0 mA |
| Bias Pin Quiescent Current | 60 µA max; IOUT = 300 mA |
| Input Pin Quiescent Current | 1.6 µA typ, 2.1 µA max; TJ = 25°C, IOUT = 0 mA |
| Input Pin Quiescent Current | 2.3 µA max; -40°C < TJ < 85°C, IOUT = 0 mA |
| Input Pin Quiescent Current | 2.6 µA max; IOUT = 0 mA |
| Input Pin Quiescent Current | 9 µA max; IOUT = 300 mA |
| VBIAS Shutdown Current | 400 nA max; -40°C < TJ < 85°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V |
| VBIAS Shutdown Current | 1200 nA max; -40°C < TJ < 125°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V |
| VIN Shutdown Current | 1 µA max; -40°C < TJ < 85°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V |
| VIN Shutdown Current | 3 µA max; -40°C < TJ < 125°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V |
| Output Current Limit | 325 mA min, 450 mA typ, 600 mA max; VOUT = 0.9 x VOUT(NOM), YKA package |
| Output Current Limit | 350 mA min, 450 mA typ, 625 mA max; VOUT = 0.9 x VOUT(NOM), DSE package |
| Short-Circuit Current Limit | 150 mA typ; VOUT = 0 V |
| VIN Dropout Voltage | 40 mV typ, 70 mV max; VIN = VOUT(NOM) - 0.1 V, IOUT = 300 mA, YKA package; not measured for VOUT < 1.0 V |
| VIN Dropout Voltage | 55 mV typ, 90 mV max; VIN = VOUT(NOM) - 0.1 V, IOUT = 300 mA, DSE package; not measured for VOUT < 1.0 V |
| VBIAS Dropout Voltage | 0.85 V typ, 1.05 V max; IOUT = 300 mA |
| VBIAS Dropout Voltage | 0.75 V typ, 0.95 V max; IOUT = 150 mA |
| VIN PSRR | 60 dB; f = 1 kHz, VOUT = 1.1 V, IOUT = 50 mA |
| VIN PSRR | 36 dB; f = 100 kHz, VOUT = 1.1 V, IOUT = 50 mA |
| VIN PSRR | 32 dB; f = 1 MHz, VOUT = 1.1 V, IOUT = 50 mA |
| VIN PSRR | 35 dB; f = 1.5 MHz, VOUT = 1.1 V, IOUT = 50 mA |
| VBIAS PSRR | 60 dB; f = 1 kHz, VOUT = 1.1 V, IOUT = 300 mA |
| VBIAS PSRR | 40 dB; f = 100 kHz, VOUT = 1.1 V, IOUT = 300 mA |
| VBIAS PSRR | 35 dB; f = 1 MHz, VOUT = 1.1 V, IOUT = 300 mA |
| Output Voltage Noise | 93.9 µVRMS; Bandwidth = 10 Hz to 100 kHz, VOUT = 1.0 V, IOUT = 50 mA |
| Bias Supply UVLO Rising Threshold | 1.46 V min, 1.54 V typ, 1.63 V max; VBIAS rising |
| Bias Supply UVLO Falling Threshold | 1.35 V min, 1.44 V typ, 1.55 V max; VBIAS falling |
| Bias Supply UVLO Hysteresis | 80 mV typ; VBIAS hysteresis |
| Input Supply UVLO Rising Threshold | 645 mV min, 675 mV typ, 710 mV max; VIN rising |
| Input Supply UVLO Falling Threshold | 565 mV min, 600 mV typ, 640 mV max; VIN falling |
| Input Supply UVLO Hysteresis | 75 mV typ; VIN hysteresis |
| Startup Time | 525 µs typ, 1200 µs max; Time from EN assertion to 0.95 x VOUT(NOM) |
| EN Logic High Voltage | 0.9 V min; Enable pin high threshold |
| EN Logic Low Voltage | 0.4 V max; Enable pin low threshold |
| EN Pin Current | 10 nA max; EN = 5.5 V |
| Pulldown Resistor | 120 ohm typ; VBIAS = 3.3 V, P version only |
| Thermal Shutdown Temperature | 160°C typ; Temperature rising |
| Thermal Shutdown Reset Temperature | 145°C typ; Temperature falling |
| Input Capacitor | 2.2 µF; Recommended operating condition |
| Bias Capacitor | 0.1 µF; Recommended operating condition |
| Output Capacitor | 2.2 to 22 µF; Recommended operating condition; maximum ESR lower than 250 mohm |
| Operating Junction Temperature | -40 to 125°C; Recommended operating condition |
| Absolute Maximum VIN | -0.3 to 3.6 V; Supply pin absolute maximum rating |
| Absolute Maximum VEN | -0.3 to 6.0 V; Enable pin absolute maximum rating |
| Absolute Maximum VBIAS | -0.3 to 6.0 V; Bias pin absolute maximum rating |
| Absolute Maximum VOUT | -0.3 to VIN + 0.3 V; Output pin absolute maximum rating; 3.6 V or VIN + 0.3 V, whichever is less |
| Storage Temperature | -65 to 150°C; Absolute maximum rating |
| HBM ESD Rating | ±1000 V; Human-body model per ANSI/ESDA/JEDEC JS-001 |
| CDM ESD Rating | ±500 V; Charged-device model per JEDEC JESD22-C101 |
| Datasheet Status | request_only |
Product Overview
The TPS7A10 is a Texas Instruments Power_Management ultra-low dropout LDO regulator for low-voltage regulated rails. It provides 300 mA maximum sourced load current with recommended VIN operation from 0.75 to 3.3 V and VBIAS operation from 1.7 to 5.5 V. Fixed output voltages cover 0.5 to 3.0 V in 50-mV steps.
Accuracy specifications include ±0.5% nominal accuracy at TJ = 25°C and ±1.5% output accuracy across -40°C to 125°C under the stated VIN, VBIAS, and 1 mA to 300 mA load conditions. The device also specifies VIN and VBIAS line regulation, load regulation, dropout voltage, current limit, short-circuit current limit, output voltage noise, PSRR, UVLO thresholds, enable thresholds, and thermal shutdown behavior.
Packaging options are WSON-6 1.50 mm x 1.50 mm and DSBGA-5 0.74 mm x 1.09 mm with 0.35-mm pitch. Recommended external components include a 2.2 µF input capacitor, 0.1 µF bias capacitor, and 2.2 to 22 µF output capacitor with ESR lower than 250 mohm. These parameters support compact power regulation designs using separate input and bias supplies.
Key Features
- 300 mA maximum sourced load current
- 0.75 to 3.3 V recommended input range
- 1.7 to 5.5 V recommended bias range
- 0.5 to 3.0 V fixed outputs in 50-mV steps
- ±1.5% output accuracy from -40°C to 125°C
- VIN dropout as low as 40 mV typical in YKA package
- VBIAS dropout 0.85 V typical at 300 mA
- VIN PSRR specified from 1 kHz to 1.5 MHz
- 93.9 µVRMS output noise over 10 Hz to 100 kHz
- Enable input with 0.9 V high and 0.4 V low thresholds
- Thermal shutdown at 160°C typical temperature rising
- WSON-6 and DSBGA-5 package options
Typical Applications
- Low-voltage regulated power rails
- 300 mA point-of-load regulation
- Separate VIN and VBIAS rail systems
- Compact WSON-6 power designs
- Compact DSBGA-5 power designs
- Enable-controlled power sequencing
- Low-noise 1.0 V output rails
- Wide-temperature junction operation
Procurement Notes
When requesting a quote for TPS7A10, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What output current does the TPS7A10 support?
The TPS7A10 supports a maximum sourced load current of 300 mA. Its current-limit specifications are also defined, including 325 mA to 600 mA for the YKA package and 350 mA to 625 mA for the DSE package when VOUT is 0.9 x VOUT(NOM).
What input and bias voltage ranges are recommended?
The recommended input voltage range is 0.75 to 3.3 V, while the recommended bias voltage range is 1.7 to 5.5 V. The device uses separate VIN and VBIAS pins, with line regulation specified for both rails under stated operating conditions.
What packages are listed for the TPS7A10?
The listed package options are WSON-6 measuring 1.50 mm x 1.50 mm and DSBGA-5 measuring 0.74 mm x 1.09 mm with 0.35-mm pitch. Package-specific specifications include output accuracy, output current limit, and VIN dropout voltage conditions.
What capacitors are recommended for TPS7A10 operation?
Recommended operating conditions specify a 2.2 µF input capacitor, a 0.1 µF bias capacitor, and a 2.2 to 22 µF output capacitor. The output capacitor condition also states that maximum ESR should be lower than 250 mohm.
What protection and threshold functions are specified?
The datasheet facts specify VIN and VBIAS UVLO rising and falling thresholds with hysteresis, enable high and low thresholds, current-limit behavior, short-circuit current limit at VOUT = 0 V, and thermal shutdown at 160°C typical with reset at 145°C typical.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 20, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.