Specifications
| Type | Description |
|---|---|
| Part Number | TS3A5223 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 10-pin µQFN / UQFN RSW, 1.80 mm x 1.40 mm nominal body |
| Switch Configuration | 2-channel SPDT bidirectional analog switch; can be used as dual 2:1 multiplexer or 1:2 dual demultiplexer |
| Supply Voltage Range | 1.65-3.6 V; recommended operating conditions |
| Logic Interface Compatibility | 1.0 V compatible; control logic supports 1 V to 3.6 V CMOS logic levels |
| Analog Voltage Range | 0 V to VCC; VCOM, VNO, VNC recommended operating range |
| Digital Logic Voltage Range | 0 V to VCC; SEL1, SEL2 recommended operating range |
| Operating Free-Air Temperature | -40 to 85 °C; recommended operating conditions |
| Positive DC Supply Absolute Maximum | -0.3 to 4.3 V; VCC absolute maximum rating; 4.3 V not rated for continuous operation |
| Analog Pin Absolute Maximum Voltage | -0.3 to 4.3 V; VCOM, VNO, VNC absolute maximum rating; 4.3 V not rated for continuous operation |
| On-State Switch Continuous Current | ±300 mA; ICOM, INO, INC absolute maximum rating |
| On-State Switch Peak Current | ±500 mA; 1 ms pulse at 10% duty cycle; ICOM, INO, INC |
| Total Device Power Dissipation | 430 mW; TA=85°C, 10-µQFN RSW package |
| Junction Temperature Range | -55 to 150 °C; absolute maximum rating |
| Storage Temperature Range | -55 to 150 °C; absolute maximum rating |
| ESD Rating HBM | ±2000 V; human-body model per ANSI/ESDA/JEDEC JS-001 |
| ESD Rating CDM | ±500 V; charged-device model per JEDEC JESD22-C101 |
| High-Level Input Voltage at VCC=3.6 V | 0.8 V min; SEL1, SEL2 inputs |
| High-Level Input Voltage at VCC=2.3 V | 0.8 V min; SEL1, SEL2 inputs |
| High-Level Input Voltage at VCC=1.8 V | 0.8 V min; SEL1, SEL2 inputs |
| Low-Level Input Voltage at VCC=3.6 V | 0.3 V max; SEL1, SEL2 inputs |
| Low-Level Input Voltage at VCC=2.3 V | 0.3 V max; SEL1, SEL2 inputs |
| Low-Level Input Voltage at VCC=1.8 V | 0.3 V max; SEL1, SEL2 inputs |
| Switch On Resistance at VCC=3.6 V | 0.45 Ω typ, 0.6 Ω max; VSEL=1 V or VCC/0 V, VS=0 to VCC, IS=100 mA |
| Switch On Resistance at VCC=2.3 V | 0.6 Ω typ, 0.8 Ω max; VSEL=1 V or VCC/0 V, VS=0 to VCC, IS=100 mA |
| Switch On Resistance at VCC=1.8 V | 0.85 Ω typ, 1.2 Ω max; VSEL=1 V or VCC/0 V, VS=0 to VCC, IS=100 mA |
| On-State Resistance Matching | 0.05 Ω typ; VCC=3.6 V, VS=2 V, 1 V, 0.8 V, or 0 V; IS=100 mA |
| On Resistance Flatness at VCC=3.6 V | 0.1 Ω typ, 0.2 Ω max; VS=0 to VCC, IS=100 mA |
| On Resistance Flatness at VCC=2.3 V | 0.15 Ω typ, 0.35 Ω max; VS=0 to VCC, IS=100 mA |
| On Resistance Flatness at VCC=1.8 V | 0.4 Ω typ, 0.65 Ω max; VS=0 to VCC, IS=100 mA |
| Off Leakage Current | 5 nA typ, 90 nA max; NC, NO pin leakage when switch is off; VCC=3.6 V, VS=0.3 or 3.0 V, VCOM=3 or 0.3 V |
| On Leakage Current | 4 nA typ, 60 nA max; NC, NO pin leakage when switch is on; VCC=3.6 V, VS=0.3 or 3.0 V, VCOM=no load |
| Select Pin Input Leakage Current | 100 nA max; VS=0 or 3.6 V |
| Quiescent Supply Current | 700 nA typ, 2000 nA max; VCC=3.6 V, VSEL=0 or VCC |
| Supply Current Change | 200 nA max; VCC=3.6 V, VSEL=1 V to VSEL=VCC |
| Logic High-to-Low Propagation Delay at VCC=3.6 V | 0.1 ns typ; RL=50 Ω, CL=35 pF |
| Logic High-to-Low Propagation Delay at VCC=2.5 V | 0.2 ns typ; RL=50 Ω, CL=35 pF |
| Logic High-to-Low Propagation Delay at VCC=1.8 V | 0.2 ns typ; RL=50 Ω, CL=35 pF |
| Logic Low-to-High Propagation Delay at VCC=3.6 V | 0.1 ns typ; RL=50 Ω, CL=35 pF |
| Logic Low-to-High Propagation Delay at VCC=2.5 V | 0.2 ns typ; RL=50 Ω, CL=35 pF |
| Logic Low-to-High Propagation Delay at VCC=1.8 V | 0.2 ns typ; RL=50 Ω, CL=35 pF |
| Turn-On Time | 70 ns typ; VCC=2.3-3.6 V, RL=50 Ω, CL=35 pF, VS=1.5 V |
| Turn-Off Time | 75 ns typ; VCC=2.3-3.6 V, RL=50 Ω, CL=35 pF, VS=1.5 V |
| Break-Before-Make Time Delay | 2 ns min, 8 ns typ; VCC=3.6 V, RL=50 Ω, CL=35 pF, VS=1.5 V |
| Charge Injection | 40 pC typ; VCC=3.6 V, CL=1 nF, VS=0 V |
| -3 dB Bandwidth | 80 MHz typ; VCC=1.65-3.6 V, RL=50 Ω, CL=35 pF |
| Channel Off Isolation | -70 dB typ; VCC=1.65-3.6 V, VS=1 Vrms, f=100 kHz |
| Channel-to-Channel Crosstalk | -75 dB typ; VCC=1.65-3.6 V, VS=1 Vrms, f=100 kHz |
| Total Harmonic Distortion | 0.01% typ; VCC=1.65-3.6 V, RL=600 Ω, VSEL=2 Vpk-pk, f=20 Hz to 20 kHz |
| Select Pin Input Capacitance | 3 pF typ; VCC=3.3 V, f=1 MHz |
| On Capacitance | 115 pF typ; NC, NO, and COM input capacitance when switch is on; VCC=3.3 V, f=1 MHz |
| Off Capacitance | 50 pF typ; NC, NO, and COM input capacitance when switch is off; VCC=3.3 V, f=1 MHz |
| Junction-to-Ambient Thermal Resistance | 92.5 °C/W; RSW UQFN, 10 pins |
| Junction-to-Case Top Thermal Resistance | 46.0 °C/W; RSW UQFN, 10 pins |
| Junction-to-Board Thermal Resistance | 44.5 °C/W; RSW UQFN, 10 pins |
| Junction-to-Top Characterization Parameter | 1.5 °C/W; RSW UQFN, 10 pins |
| Junction-to-Board Characterization Parameter | 44.5 °C/W; RSW UQFN, 10 pins |
| Junction-to-Case Bottom Thermal Resistance | 31.2 °C/W; RSW UQFN, 10 pins |
| Select Logic Function | Logic low connects COM to NC; logic high connects COM to NO; SEL1, SEL2 pin function |
| Pin Count | 10 pins; RSW UQFN package |
| Datasheet Status | request_only |
Product Overview
TS3A5223 is a Texas Instruments Signal_Chain device configured as a 2-channel SPDT bidirectional analog switch. Each channel connects COM to NC when the select logic is low and COM to NO when the select logic is high, allowing use as a dual 2:1 multiplexer or a 1:2 dual demultiplexer.
The recommended supply range is 1.65-3.6 V, with analog pins and digital select pins operating from 0 V to VCC. SEL1 and SEL2 support 1.0 V compatible CMOS logic levels across the stated control range, with 0.8 V minimum high-level input voltage and 0.3 V maximum low-level input voltage at listed VCC conditions.
The switch provides 0.45 Ω typical on resistance at VCC=3.6 V, 0.6 Ω typical at 2.3 V, and 0.85 Ω typical at 1.8 V. Signal-chain parameters include 80 MHz typical -3 dB bandwidth, -70 dB typical off isolation, -75 dB typical crosstalk, and 0.01% typical total harmonic distortion over 20 Hz to 20 kHz conditions. The 10-pin RSW UQFN package has a 1.80 mm x 1.40 mm nominal body and specified thermal metrics for board and package design.
Key Features
- 2-channel SPDT bidirectional analog switch topology
- Dual 2:1 multiplexer or 1:2 demultiplexer use
- 1.65-3.6 V recommended supply voltage range
- 1.0 V compatible CMOS select logic interface
- Analog signal range from 0 V to VCC
- 0.45 Ω typical on resistance at 3.6 V
- 80 MHz typical -3 dB signal bandwidth
- Break-before-make switching, 2 ns minimum delay
- -70 dB typical channel off isolation
- 0.01% typical total harmonic distortion
Typical Applications
- Dual analog signal multiplexing
- Dual analog signal demultiplexing
- Low-voltage CMOS-controlled signal routing
- Bidirectional analog channel switching
- Audio-band signal switching
- 80 MHz bandwidth signal paths
- COM-to-NC or COM-to-NO selection
Procurement Notes
When requesting a quote for TS3A5223, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of switch is the TS3A5223?
The TS3A5223 is a Texas Instruments 2-channel SPDT bidirectional analog switch. The extracted datasheet facts state it can be used as a dual 2:1 multiplexer or as a 1:2 dual demultiplexer.
What supply voltage range does TS3A5223 support?
The recommended operating supply voltage range is 1.65-3.6 V. The analog pins VCOM, VNO, and VNC are specified for a recommended operating range from 0 V to VCC.
How do the select inputs control the switch paths?
For SEL1 and SEL2, a logic low connects COM to NC, while a logic high connects COM to NO. The select logic supports 1.0 V compatible CMOS levels across the stated logic-control conditions.
What package is specified for TS3A5223?
The part is specified in a 10-pin µQFN / UQFN RSW package with a 1.80 mm x 1.40 mm nominal body. The extracted facts also list 10 pins for the RSW UQFN package.
What are key signal-chain performance values for TS3A5223?
Key listed signal parameters include 80 MHz typical -3 dB bandwidth, -70 dB typical channel off isolation, -75 dB typical channel-to-channel crosstalk, and 0.01% typical total harmonic distortion under the specified datasheet conditions.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 12, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.