Specifications
| Type | Description |
|---|---|
| Part Number | UCC27200 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Package / Case | D (SOIC, 8) 3.9 mm x 4.9 mm; DDA (PowerPAD SOIC, 8) 3.9 mm x 4.9 mm; DRM (VSON, 8) 4.0 mm x 4.0 mm |
| Driver configuration | Drives two N-channel MOSFETs in high-side and low-side configuration |
| Maximum boot voltage | 120 V |
| Maximum VDD voltage | 20 V |
| Negative voltage handling on HS | -5 V |
| Peak source current | 3 A; high-side and low-side gate drivers |
| Peak sink current | 3 A; high-side and low-side gate drivers |
| Typical propagation delay | 22 ns |
| Delay matching | 1 ns typ |
| Rise time | 8 ns; CLOAD=1000 pF |
| Fall time | 7 ns; CLOAD=1000 pF |
| Bootstrap diode forward voltage | 0.65 V typ; on-chip bootstrap diode |
| Bootstrap diode dynamic resistance, page 1 | 0.65 ohm typ; on-chip bootstrap diode |
| Input threshold type, UCC27200 | High-noise-immune CMOS input thresholds |
| Input threshold type, UCC27201 | TTL-compatible thresholds |
| HB pin function | High-side bootstrap supply; external bootstrap capacitor required; typical HB bypass capacitor 0.022 uF to 0.1 uF |
| VDD decoupling capacitor range | 0.22 uF to 1 uF; VDD to VSS |
| Absolute maximum VDD supply voltage | -0.3 V to 20 V; with respect to VSS |
| Absolute maximum HI/LI input voltage | -0.3 V to 20 V; with respect to VSS |
| Absolute maximum LO output voltage, DC | -0.3 V to VDD + 0.3 V; with respect to VSS |
| Absolute maximum LO output voltage, repetitive pulse | -2 V to VDD + 0.3 V; pulse <100 ns |
| Absolute maximum HO output voltage, DC | VHS - 0.3 V to VHB + 0.3 V; with respect to VSS |
| Absolute maximum HO output voltage, repetitive pulse | VHS - 2 V to VHB + 0.3 V; pulse <100 ns |
| Absolute maximum HS voltage, DC | -1 V to 120 V; with respect to VSS |
| Absolute maximum HS voltage, repetitive pulse | -5 V to 120 V; pulse <100 ns |
| Absolute maximum HB voltage | -0.3 V to 120 V; with respect to VSS |
| Absolute maximum HB-HS voltage | -0.3 V to 20 V |
| Operating junction temperature | -40°C to 150°C; absolute maximum rating |
| Storage temperature | -65°C to 150°C |
| ESD rating, HBM | +/-2000 V; ANSI/ESDA/JEDEC JS-001 |
| ESD rating, CDM | +/-1000 V; JEDEC JESD22-C101 |
| Recommended VDD supply voltage | 8 V min, 12 V nom, 17 V max; operating free-air temperature range |
| Recommended HS voltage | -1 V min, 105 V max; operating free-air temperature range |
| Recommended HS voltage, repetitive pulse | -5 V min, 110 V max; pulse <100 ns |
| Recommended HB voltage | VHS + 8.0 V min, 115 V max; operating free-air temperature range |
| HS voltage slew rate | 50 V/ns max |
| Recommended junction temperature | -40°C to 150°C |
| Thermal resistance junction-to-ambient, D SOIC | 112.5 °C/W; 8-pin D package |
| Thermal resistance junction-to-ambient, DDA PowerPAD SOIC | 44.8 °C/W; 8-pin DDA package |
| Thermal resistance junction-to-ambient, DRM VSON | 46.2 °C/W; 8-pin DRM package |
| VDD quiescent current | 0.11 mA typ, 0.8 mA max; VDD=VHB=12 V, VHS=VSS=0 V, no load, TA=TJ=-40°C to 150°C, VLI=VHI=0 V |
| VDD operating current | 1 mA typ, 3 mA max; f=500 kHz, CLOAD=0 |
| Boot voltage quiescent current | 0.065 mA typ, 0.8 mA max; VLI=VHI=0 V |
| Boot voltage operating current | 0.9 mA typ, 3 mA max; f=500 kHz, CLOAD=0 |
| HB to VSS quiescent current | 0.0005 uA typ, 1 uA max; VHS=VHB=105 V |
| HB to VSS operating current | 0.03 mA typ; f=500 kHz, CLOAD=0 |
| UCC27200 input high threshold | 6 V min, 8 V max |
| UCC27200 input low threshold | 3 V min, 5.6 V max |
| UCC27200 input hysteresis | 0.4 V typ |
| UCC27200 input pulldown resistance | 100 kohm min, 200 kohm typ, 350 kohm max; VIN=3 V |
| UCC27201 input high threshold | 1.9 V min, 2.3 V typ, 2.7 V max |
| UCC27201 input low threshold | 1.3 V min, 1.6 V typ, 1.9 V max |
| UCC27201 input hysteresis | 0.7 V typ |
| UCC27201 input pulldown resistance | 68 kohm typ; VIN=3 V |
| VDD UVLO rising threshold | 6.2 V min, 7.1 V typ, 7.8 V max |
| VDD UVLO hysteresis | 0.5 V typ |
| VHB UVLO rising threshold | 5.8 V min, 6.7 V typ, 7.2 V max |
| VHB UVLO hysteresis | 0.4 V typ |
| Bootstrap diode low-current forward voltage | 0.65 V typ, 0.85 V max; I(VDD-HB)=100 uA |
| Bootstrap diode high-current forward voltage | 0.85 V typ, 1.1 V max; I(VDD-HB)=100 mA |
| Bootstrap diode dynamic resistance, electrical characteristics | 0.65 ohm typ, 1 ohm max; Delta VF / Delta I, I(VDD-HB)=120 mA and 100 mA |
| LO low-level output voltage | 0.1 V typ, 0.4 V max; ILO=100 mA |
| LO high-level output voltage drop | 0.13 V typ, 0.42 V max; ILO=-100 mA, VLOH=VDD-VLO |
| LO peak pullup current | 3 A typ; VLO=0 V; not production tested |
| LO peak pulldown current | 3 A typ; VLO=12 V; not production tested |
| HO low-level output voltage | 0.1 V typ, 0.4 V max; IHO=100 mA |
| HO high-level output voltage drop | 0.13 V typ, 0.42 V max; IHO=-100 mA, VHOH=VHB-VHO |
| HO peak pullup current | 3 A typ; VHO=0 V; not production tested |
| HO peak pulldown current | 3 A typ; VHO=12 V; not production tested |
| LI falling to LO falling propagation delay | 22 ns typ, 50 ns max; CLOAD=0 pF, from VLIT of LI to 90% of LO falling |
| HI falling to HO falling propagation delay | 22 ns typ, 50 ns max; CLOAD=0 pF, from VIT of HI to 90% of HO falling |
| LI rising to LO rising propagation delay | 22 ns typ, 50 ns max; CLOAD=0 pF, from VHIT of LI to 10% of LO rising |
| HI rising to HO rising propagation delay | 22 ns typ, 50 ns max; CLOAD=0 pF, from VHIT of HI to 10% of HO rising |
| Delay matching, LI ON HI OFF | 1 ns typ, 7 ns max |
| Delay matching, LI OFF HI ON | 1 ns typ, 7 ns max |
| LO rise time | 8 ns typ; CLOAD=1000 pF, 10% to 90% |
| HO rise time | 8 ns typ; CLOAD=1000 pF, 10% to 90% |
| LO fall time | 7 ns typ; CLOAD=1000 pF, 10% to 90% |
| HO fall time | 7 ns typ; CLOAD=1000 pF, 10% to 90% |
| LO rise time, heavy capacitive load | 0.26 us typ, 0.6 us max; CLOAD=0.1 uF, 3 V to 9 V |
| HO rise time, heavy capacitive load | 0.26 us typ, 0.6 us max; CLOAD=0.1 uF, 3 V to 9 V |
| LO fall time, heavy capacitive load | 0.22 us typ, 0.6 us max; CLOAD=0.1 uF, 9 V to 3 V |
| HO fall time, heavy capacitive load | 0.22 us typ, 0.6 us max; CLOAD=0.1 uF, 9 V to 3 V |
| Minimum LI input pulse width affecting output | 50 ns; minimum input pulse width that changes LO output |
| Minimum HI input pulse width affecting output | 50 ns; minimum input pulse width that changes HO output |
| Bootstrap diode turnoff time | 20 ns typ; IF=20 mA, IREV=0.5 A, TA=25°C; not production tested |
| Datasheet Status | request_only |
Product Overview
The UCC27200 is a Texas Instruments 120V half-bridge gate driver in the Power_Management category. It drives two N-channel MOSFETs in a high-side and low-side configuration, with separate HO and LO outputs referenced to the bootstrap and low-side supply domains. The UCC27200 version uses high-noise-immune CMOS input thresholds, while the related UCC27201 uses TTL-compatible thresholds.
Electrical limits include 120 V maximum boot voltage, 20 V maximum VDD voltage, and -5 V repetitive-pulse handling on the HS node for pulses under 100 ns. Recommended operation specifies VDD from 8 V to 17 V, HS up to 105 V, repetitive HS pulses from -5 V to 110 V, and an HS slew rate up to 50 V/ns.
The driver provides 3 A typical peak pullup and pulldown current on both HO and LO. Timing specifications include 22 ns typical propagation delay, 1 ns typical delay matching, 8 ns rise time, and 7 ns fall time with 1000 pF load. Packages include SOIC-8, PowerPAD SOIC-8, and VSON-8 options for assembly needs.
Key Features
- Drives two N-channel MOSFETs in half-bridge configuration
- 120 V maximum boot voltage rating
- 20 V maximum VDD supply voltage rating
- 3 A peak source and sink gate-drive current
- 22 ns typical propagation delay
- 1 ns typical delay matching
- 8 ns rise time with 1000 pF load
- 7 ns fall time with 1000 pF load
- On-chip bootstrap diode with 0.65 V typical forward voltage
- High-noise-immune CMOS input thresholds for UCC27200
Typical Applications
- High-side and low-side MOSFET drive
- Half-bridge power stages
- Synchronous power converter gate drive
- Bootstrap-supplied high-side drive circuits
- Fast switching N-channel MOSFET stages
- PWM-driven power management circuits
Procurement Notes
When requesting a quote for UCC27200, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What type of driver is the UCC27200?
The UCC27200 is a Texas Instruments 120V half-bridge gate driver. It drives two N-channel MOSFETs in a high-side and low-side configuration using HO and LO gate-driver outputs.
What supply voltage range is recommended for VDD?
The recommended VDD supply voltage is 8 V minimum, 12 V nominal, and 17 V maximum over the operating free-air temperature range. The absolute maximum VDD supply rating is -0.3 V to 20 V with respect to VSS.
What are the typical switching timing specifications?
Typical propagation delay is 22 ns, with 1 ns typical delay matching. With a 1000 pF load, the listed typical rise time is 8 ns and the typical fall time is 7 ns for the driver outputs.
Which packages are listed for the UCC27200?
The listed package options are D SOIC-8 at 3.9 mm x 4.9 mm, DDA PowerPAD SOIC-8 at 3.9 mm x 4.9 mm, and DRM VSON-8 at 4.0 mm x 4.0 mm.
What input threshold type applies to UCC27200?
The UCC27200 uses high-noise-immune CMOS input thresholds. Its listed input high threshold is 6 V minimum and 8 V maximum, and its input low threshold is 3 V minimum and 5.6 V maximum.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 13, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.