Specifications
| Type | Description |
|---|---|
| Part Number | UCC27211 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Package / Case | SOIC-8 D 4.9mm x 3.9mm; PowerPAD SOIC-8 DDA 4.9mm x 3.9mm; VSON-8 DRM 4.0mm x 4.0mm; WSON-10 DPR 4.0mm x 4.0mm |
| Component Type | Power_IC |
| Driver Configuration | High-side and low-side half-bridge driver for two N-channel MOSFETs; Independent HI and LI inputs |
| Maximum Boot Voltage | 120 V DC; HB bootstrap voltage rating |
| Peak Source Current | 3.7 A; Gate driver output pull-up current |
| Peak Sink Current | 4.5 A; Gate driver output pull-down current |
| Recommended VDD Supply Voltage | 8 V min, 12 V typ, 17 V max; Operating free-air temperature range, referenced to VSS |
| Absolute Maximum VDD Supply Voltage | -0.3 V min, 20 V max; Referenced to VSS |
| Input Voltage Range Absolute Maximum | -10 V min, 20 V max; HI and LI input pins |
| Recommended HS Voltage | -1 V min, 105 V max; Operating free-air temperature range |
| Recommended HS Repetitive Pulse Voltage | -(24 V - VDD) min, 110 V max; Repetitive pulse < 100 ns; characterized, not production tested |
| HS Slew Rate | 50 V/ns max; Recommended operating condition |
| Operating Junction Temperature | -40 °C min, 150 °C max; Recommended and absolute maximum operating range |
| Storage Temperature | -65 °C min, 150 °C max; Absolute maximum rating |
| HB Voltage Absolute Maximum | -0.3 V min, 120 V max; Referenced to VSS unless otherwise noted |
| HB-HS Voltage Absolute Maximum | -0.3 V min, 20 V max; Bootstrap supply differential |
| LO Output Voltage Absolute Maximum | -0.3 V min, VDD + 0.3 V max; DC output voltage on LO |
| LO Output Repetitive Pulse Voltage Absolute Maximum | -2 V min, VDD + 0.3 V max; Repetitive pulse < 100 ns |
| HO Output Voltage Absolute Maximum | VHS - 0.3 V min, VHB + 0.3 V max; DC output voltage on HO |
| HO Output Repetitive Pulse Voltage Absolute Maximum | VHS - 2 V min, VHB + 0.3 V max; Repetitive pulse < 100 ns |
| HS Voltage Absolute Maximum | -1 V min, 115 V max; DC voltage on HS |
| HS Repetitive Pulse Voltage Absolute Maximum | -(24 V - VDD) min, 115 V max; Repetitive pulse < 100 ns |
| HBM ESD Rating | ±2000 V; Human-body model per ANSI/ESDA/JEDEC JS-001 |
| CDM ESD Rating | ±1000 V; Charged-device model per JEDEC JESD22C101 |
| VDD Quiescent Current | 0.11 mA typ, 0.19 mA max; VDD = VHB = 12 V, VHS = VSS = 0 V, VLI = VHI = 0 V, no load, TA = TJ = -40 °C to 150 °C |
| VDD Operating Current | 1.4 mA typ, 3 mA max; f = 500 kHz, CLOAD = 0 pF |
| Boot Voltage Quiescent Current | 0.065 mA typ, 0.12 mA max; VLI = VHI = 0 V |
| Boot Voltage Operating Current | 1.3 mA typ, 3 mA max; f = 500 kHz, CLOAD = 0 pF |
| HB to VSS Quiescent Current | 0.0005 µA typ, 1 µA max; VHS = VHB = 105 V |
| HB to VSS Operating Current | 0.03 mA typ, 1 mA max; f = 500 kHz, CLOAD = 0 pF |
| HI Input High Threshold | 1.7 V min, 2.3 V typ, 2.7 V max; VDD = VHB = 12 V, VHS = VSS = 0 V |
| LI Input High Threshold | 1.7 V min, 2.3 V typ, 2.7 V max; VDD = VHB = 12 V, VHS = VSS = 0 V |
| HI Input Low Threshold | 1.2 V min, 1.6 V typ, 1.9 V max; VDD = VHB = 12 V, VHS = VSS = 0 V |
| LI Input Low Threshold | 1.2 V min, 1.6 V typ, 1.9 V max; VDD = VHB = 12 V, VHS = VSS = 0 V |
| HI Input Hysteresis | 0.7 V typ; TTL-compatible input version |
| LI Input Hysteresis | 0.7 V typ; TTL-compatible input version |
| HI Input Pulldown Resistance | 68 kΩ typ; VIN = 3 V |
| LI Input Pulldown Resistance | 68 kΩ typ; VIN = 3 V |
| VDD UVLO Rising Threshold | 6.2 V min, 7 V typ, 7.8 V max; Undervoltage protection |
| VDD UVLO Hysteresis | 0.5 V typ; Undervoltage protection |
| VHB UVLO Rising Threshold | 5.6 V min, 6.7 V typ, 7.9 V max; Undervoltage protection |
| VHB UVLO Hysteresis | 1.1 V typ; Undervoltage protection |
| Bootstrap Diode Low-Current Forward Voltage | 0.65 V typ, 0.85 V max; I(VDD-HB) = 100 µA |
| Bootstrap Diode High-Current Forward Voltage | 0.9 V typ, 1.05 V max; I(VDD-HB) = 100 mA |
| Bootstrap Diode Dynamic Resistance | 0.3 Ω min, 0.55 Ω typ, 0.85 Ω max; I(VDD-HB) = 160 mA and 180 mA; ΔVF/ΔI |
| LO Low-Level Output Voltage | 0.07 V typ, 0.19 V max; ILO = 100 mA |
| LO High-Level Output Voltage Drop | 0.11 V typ, 0.29 V max; ILO = -100 mA, VLOH = VDD - VLO |
| LO Peak Pullup Current | 3.7 A typ; VLO = 0 V; parameter not tested in production |
| LO Peak Pulldown Current | 4.5 A typ; VLO = 12 V; parameter not tested in production |
| HO Low-Level Output Voltage | 0.07 V typ, 0.19 V max; IHO = 100 mA |
| HO High-Level Output Voltage Drop | 0.11 V typ, 0.29 V max; IHO = -100 mA, VHOH = VHB - VHO |
| HO Peak Pullup Current | 3.7 A typ; VHO = 0 V; parameter not tested in production |
| HO Peak Pulldown Current | 4.5 A typ; VHO = 12 V; parameter not tested in production |
| LI Falling to LO Falling Propagation Delay | 10 ns min, 19 ns typ, 30 ns max; CLOAD = 0 pF, from VLIT of LI to 90% of LO falling |
| HI Falling to HO Falling Propagation Delay | 10 ns min, 19 ns typ, 30 ns max; CLOAD = 0 pF, from VLIT of HI to 90% of HO falling |
| LI Rising to LO Rising Propagation Delay | 10 ns min, 20 ns typ, 40 ns max; CLOAD = 0 pF, from VHIT of LI to 10% of LO rising |
| HI Rising to HO Rising Propagation Delay | 10 ns min, 20 ns typ, 40 ns max; CLOAD = 0 pF, from VHIT of HI to 10% of HO rising |
| Delay Matching LI On HI Off | 4 ns typ, 9.5 ns max; TJ = 25 °C |
| Delay Matching LI On HI Off | 4 ns typ, 17 ns max; TJ = -40 °C to 150 °C |
| Delay Matching LI Off HI On | 4 ns typ, 9.5 ns max; TJ = 25 °C |
| Delay Matching LI Off HI On | 4 ns typ, 17 ns max; TJ = -40 °C to 150 °C |
| LO Rise Time | 7.2 ns typ; CLOAD = 1000 pF, from 10% to 90% |
| HO Rise Time | 7.2 ns typ; CLOAD = 1000 pF, from 10% to 90% |
| LO Fall Time | 5.5 ns typ; CLOAD = 1000 pF, from 10% to 90% |
| HB Bypass Capacitor Range | 0.022 µF to 0.1 µF; External bootstrap capacitor required; connect positive side to HB |
| VDD Decoupling Capacitor Range | 0.22 µF to 4.7 µF; Decouple VDD to VSS |
| D Package Junction-to-Ambient Thermal Resistance | 112.5 °C/W; SOIC-8 package |
| DDA Package Junction-to-Ambient Thermal Resistance | 44.8 °C/W; PowerPAD SOIC-8 package |
| DRM Package Junction-to-Ambient Thermal Resistance | 46.2 °C/W; VSON-8 package |
| DPR Package Junction-to-Ambient Thermal Resistance | 46.1 °C/W; WSON-10 package |
| Datasheet Status | request_only |
Product Overview
The UCC27211 is a Texas Instruments half-bridge MOSFET gate driver in the Power_Management category. It drives high-side and low-side positions for two N-channel MOSFETs and uses independent HI and LI inputs, allowing separate control of the HO and LO outputs within the extracted operating limits.
The driver supports a 120 V DC HB bootstrap voltage rating, 3.7 A typical peak pullup current, and 4.5 A typical peak pulldown current. Recommended operation includes VDD from 8 V to 17 V, HS from -1 V to 105 V, repetitive HS pulses up to 110 V, and a maximum HS slew rate of 50 V/ns. Propagation delays are specified from 10 ns minimum to 40 ns maximum depending on input transition and output path.
Package options include SOIC-8 D, PowerPAD SOIC-8 DDA, VSON-8 DRM, and WSON-10 DPR. Assembly guidance from the extracted facts includes a 0.022 µF to 0.1 µF HB bypass capacitor and 0.22 µF to 4.7 µF VDD decoupling capacitor.
Key Features
- High-side and low-side driver for two N-channel MOSFETs
- Independent HI and LI input control pins
- 120 V DC HB bootstrap voltage rating
- 3.7 A peak source gate-drive current
- 4.5 A peak sink gate-drive current
- Recommended VDD operating range from 8 V to 17 V
- 50 V/ns maximum recommended HS slew rate
- VDD and VHB undervoltage lockout thresholds specified
- Integrated bootstrap diode with characterized forward voltage
- SOIC, PowerPAD SOIC, VSON, and WSON package options
Typical Applications
- Half-bridge MOSFET power stages
- High-side and low-side gate drive
- Two N-channel MOSFET bridge control
- Bootstrap-supplied high-side drive
- Fast-switching power conversion stages
- TTL-compatible input driver interfaces
Procurement Notes
When requesting a quote for UCC27211, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What type of driver is the UCC27211?
The UCC27211 is a Texas Instruments half-bridge MOSFET gate driver for high-side and low-side drive of two N-channel MOSFETs. It uses independent HI and LI inputs for the high-side and low-side channels.
What supply voltage range is recommended for VDD?
The recommended VDD supply voltage is 8 V minimum, 12 V typical, and 17 V maximum, referenced to VSS over the operating free-air temperature range stated in the extracted datasheet facts.
What gate-drive currents are specified for UCC27211?
The extracted facts specify 3.7 A typical peak pullup current and 4.5 A typical peak pulldown current. The same values are listed for LO and HO peak drive current parameters under the stated output test conditions.
Which package options are listed for UCC27211?
The listed package options are SOIC-8 D 4.9mm x 3.9mm, PowerPAD SOIC-8 DDA 4.9mm x 3.9mm, VSON-8 DRM 4.0mm x 4.0mm, and WSON-10 DPR 4.0mm x 4.0mm.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 13, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.