Specifications
| Type | Description |
|---|---|
| Part Number | UCC27524 |
| Manufacturer | Texas Instruments |
| Product Type | LDO Regulator |
| Category | Power Management |
| Component Type | Power_IC |
| Package / Case | SOIC-8 D 4.90 mm x 3.91 mm; HVSSOP-8 DGN 3.00 mm x 3.00 mm; WSON-8 DSD 3.00 mm x 3.00 mm |
| Gate Drive Channels | 2 independent channels; dual-channel device |
| Driver Polarity | Dual non-inverting; UCC27524 device |
| Peak Source Current | 5 A; gate-drive output capability |
| Peak Sink Current | 5 A; gate-drive output capability |
| Single Supply Range | 4.5 V to 18 V; recommended supply operating range |
| Typical Propagation Delay | 17 ns; typical condition |
| Typical Rise Time | 6 ns; typical condition |
| Typical Fall Time | 10 ns; typical condition |
| Typical Delay Matching | 1 ns; between two channels |
| Input Negative Voltage Capability | -5 V; input pins, robustness feature |
| Operating Junction Temperature Range | -40 degC to 150 degC; device operating junction temperature range |
| Supply Voltage Absolute Maximum | -0.3 V to 20 V; VDD, over operating free-air temperature range |
| Output Voltage Absolute Maximum | -0.3 V to VDD + 0.3 V; OUTA, OUTB DC voltage |
| Output Repetitive Pulse Voltage Absolute Maximum | -2 V to VDD + 0.3 V; OUTA, OUTB, repetitive pulse less than 200 ns |
| Output Continuous Source/Sink Current Absolute Maximum | 0.3 A; IOUT_DC |
| Output Pulsed Source/Sink Current Absolute Maximum | 5 A; 0.5 us pulse, IOUT_pulsed |
| Input and Enable Voltage Absolute Maximum | -5 V to 20 V; INA, INB, ENA, ENB; D and DGN packages |
| Input and Enable Voltage Absolute Maximum | -0.3 V to 20 V; INA, INB, ENA, ENB; DSD package |
| Storage Temperature Range | -65 degC to 150 degC; Tstg |
| HBM ESD Rating | +/-2000 V; D and DGN packages, ANSI/ESDA/JEDEC JS-001 |
| HBM ESD Rating | +/-4000 V; DSD package, ANSI/ESDA/JEDEC JS-001 |
| CDM ESD Rating | +/-1000 V; JEDEC JESD22-C101 |
| Recommended Supply Voltage | 4.5 V min, 12 V nom, 18 V max; VDD, recommended operating conditions |
| Recommended Operating Junction Temperature | -40 degC to 140 degC; recommended operating conditions |
| Recommended Input Voltage | -2 V to 18 V; INA, INB; D and DGN packages |
| Recommended Input Voltage | 0 V to 18 V; INA, INB; DSD package |
| Recommended Enable Voltage | -2 V to 18 V; ENA, ENB |
| Junction-to-Ambient Thermal Resistance | 48.9 degC/W; DGN package, RthetaJA |
| Junction-to-Ambient Thermal Resistance | 126.4 degC/W; D package, RthetaJA |
| Junction-to-Ambient Thermal Resistance | 46.7 degC/W; DSD package, RthetaJA |
| VDD Quiescent Supply Current | 300 uA typ, 450 uA max; D/DGN, VINx=3.3 V, VDD=3.4 V, ENx=VDD |
| VDD Static Supply Current | 0.6 mA typ, 1.0 mA max; D/DGN, VINx=3.3 V, ENx=VDD |
| VDD Static Supply Current | 0.7 mA typ, 1.0 mA max; D/DGN, VINx=0 V, ENx=VDD |
| VDD Operating Current | 3.2 mA typ, 3.8 mA max; D/DGN, fSW=1000 kHz, ENx=VDD, VINx=0 V to 3.3 V PWM |
| VDD Disable Current | 0.8 mA typ, 1.1 mA max; D/DGN, VINx=3.3 V, ENx=0 V |
| Startup Current | 55 uA min, 110 uA typ, 175 uA max; DSD, VDD=3.4 V, INA=VDD, INB=VDD |
| Startup Current | 25 uA min, 75 uA typ, 145 uA max; DSD, VDD=3.4 V, INA=GND, INB=GND |
| VDD UVLO Rising Threshold | 3.8 V min, 4.1 V typ, 4.4 V max; D/DGN packages |
| VDD UVLO Falling Threshold | 3.5 V min, 3.8 V typ, 4.1 V max; D/DGN packages |
| VDD UVLO Hysteresis | 0.3 V typ; D/DGN packages |
| Supply Start Threshold | 3.91 V min, 4.2 V typ, 4.5 V max; DSD, TJ=25 degC |
| Supply Start Threshold | 3.7 V min, 4.2 V typ, 4.65 V max; DSD, TJ=-40 degC to 140 degC |
| Minimum Operating Voltage After Supply Start | 3.4 V min, 3.9 V typ, 4.4 V max; DSD, VOFF |
| Supply Voltage Hysteresis | 0.2 V min, 0.3 V typ, 0.5 V max; DSD, VDD_H |
| Input Signal High Threshold | 1.8 V min, 2.0 V typ, 2.3 V max; D/DGN, output high, ENx=HIGH |
| Input Signal Low Threshold | 0.8 V min, 1.0 V typ, 1.2 V max; D/DGN, output low, ENx=HIGH |
| Input Signal Hysteresis | 1 V typ; D/DGN, INA/INB |
| Input Pin Pulldown Resistor | 120 kOhm typ; D/DGN, INx=3.3 V |
| Input Signal High Threshold | 1.9 V min, 2.1 V typ, 2.3 V max; DSD, output high for non-inverting input pins |
| Input Signal Low Threshold | 1.0 V min, 1.2 V typ, 1.4 V max; DSD, output low for non-inverting input pins |
| Input Hysteresis | 0.7 V min, 0.9 V typ, 1.1 V max; DSD, INA/INB |
| Enable Signal High Threshold | 1.8 V min, 2.0 V typ, 2.3 V max; D/DGN, output high, INx=HIGH |
| Enable Signal Low Threshold | 0.8 V min, 1.0 V typ, 1.2 V max; D/DGN, output low, INx=HIGH |
| Enable Signal Hysteresis | 1 V typ; D/DGN, ENA/ENB |
| Enable Pin Pullup Resistance | 200 kOhm typ; D/DGN, ENx=0 V |
| Enable Signal High Threshold | 1.9 V min, 2.1 V typ, 2.3 V max; DSD, output enabled |
| Enable Signal Low Threshold | 0.95 V min, 1.15 V typ, 1.35 V max; DSD, output disabled |
| Enable Hysteresis | 0.7 V min, 0.95 V typ, 1.1 V max; DSD, ENA/ENB |
| Peak Output Source Current | 5 A; D/DGN, VDD=12 V, CVDD=10 uF, CL=0.1 uF, f=1 kHz |
| Peak Output Sink Current | -5 A; D/DGN, VDD=12 V, CVDD=10 uF, CL=0.1 uF, f=1 kHz |
| Output Pullup Resistance | 5 Ohm typ, 8.5 Ohm max; D/DGN, IOUT=-50 mA |
| Output Pulldown Resistance | 0.6 Ohm typ, 1.1 Ohm max; D/DGN, IOUT=50 mA |
| Sink/Source Peak Current | +/-5 A; DSD, CLOAD=0.22 uF, FSW=1 kHz |
| High Output Voltage Drop | 0.075 V typ; DSD, VDD-VOH, IOUT=-10 mA |
| Low Output Voltage | 0.01 V typ; DSD, IOUT=10 mA |
| Output Pullup Resistance | 2.5 Ohm min, 5 Ohm typ, 7.5 Ohm max; DSD, IOUT=-10 mA |
| Output Pulldown Resistance | 0.15 Ohm min, 0.5 Ohm typ, 1 Ohm max; DSD, IOUT=10 mA |
| Rise Time | 6 ns typ, 10 ns max; D/DGN, CLOAD=1.8 nF, 20% to 80%, VIN=0 V to 3.3 V |
| Fall Time | 10 ns typ, 14 ns max; D/DGN, CLOAD=1.8 nF, 90% to 10%, VIN=0 V to 3.3 V |
| Turn-On Propagation Delay | 17 ns typ, 27 ns max; D/DGN, CLOAD=1.8 nF, input rise at VINx_H to 10% output rise, VIN=0 V to 3.3 V, FSW=500 kHz, 50% duty cycle, TJ=125 degC |
| Datasheet Status | request_only |
Product Overview
The UCC27524 is a Texas Instruments Power_Management IC configured as a dual low-side gate driver. It provides 2 independent channels with dual non-inverting driver polarity, supporting 5 A peak source current and 5 A peak sink current for gate-drive output operation.
The recommended VDD operating range is 4.5 V to 18 V, with 12 V nominal operation specified in the recommended conditions. Timing parameters include 17 ns typical propagation delay, 6 ns typical rise time, 10 ns typical fall time, and 1 ns typical delay matching between the two channels.
Package options include SOIC-8 D, HVSSOP-8 DGN, and WSON-8 DSD footprints. Thermal resistance is package dependent, with RthetaJA values of 126.4 degC/W for D, 48.9 degC/W for DGN, and 46.7 degC/W for DSD. The device supports low-side gate-drive assemblies where package size, operating junction temperature, input threshold behavior, enable control, UVLO behavior, and pulsed output current limits must be accounted for.
Key Features
- 2 independent low-side gate-drive channels
- Dual non-inverting driver polarity for UCC27524
- 5 A peak source and sink drive capability
- 4.5 V to 18 V recommended VDD range
- 17 ns typical propagation delay
- 6 ns typical rise time and 10 ns typical fall time
- 1 ns typical delay matching between channels
- -40 degC to 150 degC operating junction range
- Input pins support -5 V negative voltage capability
- SOIC-8, HVSSOP-8, and WSON-8 package options
Typical Applications
- Dual low-side gate driving
- Power MOSFET gate drive stages
- PWM power switching circuits
- Two-channel gate-drive assemblies
- Enable-controlled power switching
- Fast low-side switching outputs
- Compact WSON gate-driver layouts
Procurement Notes
When requesting a quote for UCC27524, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For power IC and power device sourcing, voltage rating, current rating, power dissipation, package thermal performance, protection features, qualification grade and application conditions should be reviewed before approval.
FAQ
What type of device is the UCC27524?
The UCC27524 is a Texas Instruments dual low-side gate driver in the Power_Management category. It has 2 independent channels and uses dual non-inverting driver polarity.
What supply range is recommended for UCC27524 operation?
The recommended supply range is 4.5 V to 18 V, with 12 V listed as the nominal recommended VDD condition. Absolute maximum VDD is specified from -0.3 V to 20 V.
What output drive current does the UCC27524 support?
The device supports 5 A peak source current and 5 A peak sink current as gate-drive output capability. The absolute maximum pulsed source or sink current is also 5 A for a 0.5 us pulse.
Which package options are listed for the UCC27524?
Package options include SOIC-8 D at 4.90 mm x 3.91 mm, HVSSOP-8 DGN at 3.00 mm x 3.00 mm, and WSON-8 DSD at 3.00 mm x 3.00 mm.
What timing parameters are specified for the UCC27524?
Typical timing includes 17 ns propagation delay, 6 ns rise time, 10 ns fall time, and 1 ns typical delay matching between the two channels.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: July 13, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.