Specifications
| Type | Description |
|---|---|
| Part Number | AD7401YRWZ-REEL |
| Manufacturer | Analog Devices |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Package / Case | 16-lead SOIC |
| External Clock Rate | 20 MHz max; maximum external/master clock input frequency |
| Modulator Order | Second-order sigma-delta; device architecture |
| Resolution | 16 bits min; filter output truncated to 16 bits |
| No Missing Codes | 16 bits; guaranteed by DNL specification |
| Integral Nonlinearity | ±15 LSB max; ±2 LSB typ; -40°C to +85°C, fMCLK=20 MHz max |
| Integral Nonlinearity | ±25 LSB max; >85°C to 105°C |
| Integral Nonlinearity | ±55 LSB max; fMCLK=20 MHz max, VIN+=-250 mV to +250 mV |
| Differential Nonlinearity | ±0.9 LSB max; guaranteed no missed codes to 16 bits, fMCLK=20 MHz max, VIN+=-250 mV to +250 mV |
| Offset Error | ±0.6 mV max; fMCLK=20 MHz max, VIN+=-250 mV to +250 mV |
| Offset Error | ±50 µV typ; TA=25°C |
| Offset Drift vs Temperature | 3.5 µV/°C max; 1 µV/°C typ; -40°C to +105°C |
| Offset Drift vs VDD1 | 120 µV/V typ; supply variation on VDD1 |
| Gain Error | ±1.6 mV max; -40°C to +85°C |
| Gain Error | ±2 mV max; >85°C to 105°C |
| Gain Error | ±1 mV typ; fMCLK=20 MHz max, VIN+=-250 mV to +250 mV |
| Gain Error Drift vs Temperature | 23 µV/°C typ; -40°C to +105°C |
| Gain Error Drift vs VDD1 | 110 µV/V typ; supply variation on VDD1 |
| Analog Input Voltage Range | ±200 mV min/max; ±320 mV full scale; specified performance range |
| Dynamic Input Current | ±9 µA max; VIN+=400 mV, VIN-=0 V |
| DC Leakage Current | ±0.5 µA max; analog input |
| Input Capacitance | 10 pF typ; analog input |
| SINAD | 70 dB min; VIN+=5 kHz, 400 mV p-p sine; -40°C to +85°C; fMCLK=9 MHz to 20 MHz |
| SINAD | 68 dB min; VIN+=5 kHz, 400 mV p-p sine; -40°C to +85°C; fMCLK=5 MHz to <9 MHz |
| SINAD | 65 dB min; VIN+=5 kHz, 400 mV p-p sine; >85°C to 105°C |
| SINAD | 81 dB typ; VIN+=5 kHz, 400 mV p-p sine |
| Signal-to-Noise Ratio | 80 dB min; 82 dB typ; -40°C to +105°C |
| Total Harmonic Distortion | -92 dB typ; fMCLK=20 MHz max, VIN+=-250 mV to +250 mV |
| Spurious-Free Dynamic Range | -92 dB typ; peak harmonic or spurious noise |
| Effective Number of Bits | 11.5 bits; dynamic performance |
| Isolation Transient Immunity | 25 kV/µs min; 30 kV/µs typ; dynamic specification |
| Logic Input High Voltage | 0.8 × VDD2 V min; VIH |
| Logic Input Low Voltage | 0.2 × VDD2 V max; VIL |
| Logic Input Current | ±0.5 µA max; IIN |
| Logic Input Capacitance | 10 pF max; sample tested during initial release |
| Logic Output High Voltage | VDD2 - 0.1 V min; IO=-200 µA |
| Logic Output Low Voltage | 0.4 V max; IO=+200 µA |
| VDD1 Supply Range | 4.5 V min, 5.25 V max; power requirement |
| VDD2 Supply Range | 3 V min, 5.5 V max; power requirement, serial I/O supply |
| IDD1 Supply Current | 12 mA max; VDD1=5.25 V |
| IDD2 Supply Current | 8 mA max at VDD2=5.5 V; 4 mA max at VDD2=3.3 V |
| Data Access Time | 25 ns max; after MCLK rising edge |
| Data Hold Time | 15 ns min; after MCLK rising edge |
| Master Clock Low Time | 0.4 × tMCLKIN ns min; timing specification |
| Master Clock High Time | 0.4 × tMCLKIN ns min; timing specification |
| Operating Temperature Range | -40°C to +105°C; specified operating range |
| Input-to-Output Momentary Withstand Voltage | 3750 V rms min; 1-minute duration |
| Clearance | 7.46 mm min; minimum external air gap, input terminals to output terminals |
| Creepage | 8.1 mm min; minimum external tracking path along body |
| Internal Clearance | 0.017 mm min; insulation distance through insulation |
| Comparative Tracking Index | >175 V; DIN IEC 112/VDE 0303 Part 1 |
| Maximum Working Insulation Voltage | 891 V peak; DIN V VDE V 0884-10 insulation characteristic |
| Highest Allowable Overvoltage | 6000 V peak; transient overvoltage, tTR=10 sec |
| Safety-Limiting Case Temperature | 150°C; maximum value allowed in event of failure |
| Safety-Limiting Side 1 Current | 265 mA; maximum value allowed in event of failure |
| Safety-Limiting Side 2 Current | 335 mA; maximum value allowed in event of failure |
| Insulation Resistance | >10^9 Ω; TS, VIO=500 V |
| Absolute Maximum VDD1 to GND1 | -0.3 V to +6.5 V; TA=25°C unless otherwise noted |
| Absolute Maximum VDD2 to GND2 | -0.3 V to +6.5 V; TA=25°C unless otherwise noted |
| Absolute Maximum Analog Input Voltage | -0.3 V to VDD1 + 0.3 V; relative to GND1 |
| Storage Temperature Range | -65°C to +150°C; absolute maximum rating |
| Junction Temperature | 150°C; absolute maximum rating |
| Thermal Impedance Theta JA | 89.2°C/W; SOIC package |
| Thermal Impedance Theta JC | 55.6°C/W; SOIC package |
| Input-to-Output Resistance | 10^12 Ω; RI-O absolute maximum ratings table |
| Input-to-Output Capacitance | 1.7 pF typ; f=1 MHz |
| ESD Rating | 1.5 kV; absolute maximum ratings |
| Datasheet Status | request_only |
Product Overview
AD7401YRWZ-REEL is an Analog Devices isolated sigma-delta modulator for Signal_Chain designs. Its device architecture is a second-order sigma-delta modulator, and the extracted datasheet facts specify a maximum external/master clock input frequency of 20 MHz. The filter output is truncated to a minimum 16-bit resolution, with no missing codes to 16 bits guaranteed by the DNL specification.
The analog input performance is centered on a specified ±200 mV input range, with ±320 mV full scale noted in the description. Extracted dynamic parameters include 81 dB typical SINAD, 80 dB minimum and 82 dB typical SNR, -92 dB typical total harmonic distortion, -92 dB typical spurious-free dynamic range, and 11.5 effective number of bits.
The part is supplied in a 16-lead SOIC package and operates across -40°C to +105°C. Isolation-related facts include 3750 V rms minimum input-to-output momentary withstand voltage for 1 minute, 7.46 mm minimum clearance, 8.1 mm minimum creepage, 891 V peak maximum working insulation voltage, and 25 kV/µs minimum transient immunity. These parameters support isolated measurement, differential input monitoring, and signal-chain conversion designs.
Key Features
- Second-order sigma-delta isolated modulator architecture
- External master clock input supports 20 MHz maximum
- Minimum 16-bit output resolution after filter truncation
- No missing codes guaranteed to 16 bits by DNL
- Specified ±200 mV analog input performance range
- Typical 81 dB SINAD with 5 kHz sine input
- 80 dB minimum signal-to-noise ratio over temperature
- 25 kV/µs minimum isolation transient immunity
- VDD1 operates from 4.5 V to 5.25 V
- VDD2 serial I/O supply operates from 3 V to 5.5 V
- 3750 V rms minimum input-to-output withstand voltage
- -40°C to +105°C specified operating temperature range
Typical Applications
- Isolated signal-chain measurement
- Differential low-voltage input monitoring
- Sigma-delta conversion stages
- Isolated data acquisition inputs
- Clocked digital output measurement paths
- Systems requiring 3750 V rms isolation
- Wide-temperature signal monitoring
Procurement Notes
When requesting a quote for AD7401YRWZ-REEL, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of device is AD7401YRWZ-REEL?
AD7401YRWZ-REEL is an Analog Devices isolated sigma-delta modulator in the Signal_Chain category. The extracted datasheet facts identify it as a second-order sigma-delta architecture supplied in a 16-lead SOIC package.
What clock rate does AD7401YRWZ-REEL support?
The maximum external or master clock input frequency is specified as 20 MHz. Timing facts also list 25 ns maximum data access time and 15 ns minimum data hold time after the MCLK rising edge.
What input range is specified for AD7401YRWZ-REEL?
The specified analog input voltage performance range is ±200 mV, with ±320 mV full scale noted in the description. Analog input facts also include 10 pF typical input capacitance and ±0.5 µA maximum dc leakage current.
What isolation ratings are listed for this part?
Extracted isolation facts include 3750 V rms minimum input-to-output momentary withstand voltage for 1 minute, 25 kV/µs minimum transient immunity, 7.46 mm minimum clearance, 8.1 mm minimum creepage, and 891 V peak maximum working insulation voltage.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: August 17, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.