Specifications
| Type | Description |
|---|---|
| Part Number | AD7401YRWZ-REEL7 |
| Manufacturer | Texas Instruments |
| Product Type | Operational Amplifier |
| Category | Signal Chain |
| Inferred Category | Signal_Chain |
| Component Type | Other |
| Package / Case | 16-Lead SOIC_W wide body, package option RW-16; body 10.10-10.50 mm x 7.40-7.60 mm, 1.27 mm pitch |
| Datasheet Manufacturer Identification | Analog Devices; datasheet and ordering guide identify AD7401, conflicting with supplied manufacturer Texas Instruments |
| Converter Architecture | Second-order sigma-delta modulator |
| Output Data Format | High speed 1-bit data stream; analog input converted to density-of-ones serial stream |
| External Clock Rate | 20 MHz max, MCLKIN master clock input |
| Resolution | 16 bits min; filter output truncated to 16 bits |
| No Missing Codes | 16 bits, guaranteed by differential nonlinearity specification |
| Integral Nonlinearity | ±15 LSB max, ±2 LSB typ; -40°C to +85°C, fMCLK up to 20 MHz |
| Integral Nonlinearity | ±25 LSB max; >85°C to 105°C |
| Differential Nonlinearity | ±0.9 LSB max; guaranteed no missing codes to 16 bits, fMCLK up to 20 MHz, VIN+ = -250 mV to +250 mV |
| Offset Error | ±0.6 mV max; ±50 µV typ; max at fMCLK up to 20 MHz, VIN+ = -250 mV to +250 mV; typ at TA = 25°C |
| Offset Drift vs Temperature | 3.5 µV/°C max; 1 µV/°C typ; -40°C to +105°C |
| Offset Drift vs VDD1 | 120 µV/V typ; VDD1 supply variation |
| Gain Error | ±1.6 mV max; ±1 mV typ; -40°C to +85°C; typ at fMCLK up to 20 MHz, VIN+ = -250 mV to +250 mV |
| Gain Error | ±2 mV max; >85°C to 105°C |
| Gain Error Drift vs Temperature | 23 µV/°C typ; -40°C to +105°C |
| Specified Analog Input Range | ±200 mV; for specified performance, VIN− = 0 V single-ended in specification table |
| Full-Scale Analog Input Range | ±320 mV; absolute full-scale analog input range |
| Dynamic Input Current | ±9 µA max; VIN+ = 400 mV, VIN− = 0 V |
| DC Leakage Current | ±0.5 µA max; analog input |
| Input Capacitance | 10 pF typ; analog input |
| SINAD | 70 dB min; 81 dB typ; VIN+ = 5 kHz, 400 mV p-p sine, -40°C to +85°C, fMCLK = 9 MHz to 20 MHz |
| SINAD | 68 dB min; VIN+ = 5 kHz, 400 mV p-p sine, -40°C to +85°C, fMCLK = 5 MHz to <9 MHz |
| Signal-to-Noise Ratio | 80 dB min; 82 dB typ; -40°C to +105°C |
| Total Harmonic Distortion | -92 dB typ; fMCLK up to 20 MHz, VIN+ = -250 mV to +250 mV |
| Spurious-Free Dynamic Range | -92 dB typ; peak harmonic or spurious noise |
| Effective Number of Bits | 11.5 bits; dynamic specifications |
| Isolation Transient Immunity | 25 kV/µs min; 30 kV/µs typ; dynamic specifications |
| Logic Input High Voltage | 0.8 x VDD2 min; VIH |
| Logic Input Low Voltage | 0.2 x VDD2 max; VIL |
| Logic Output High Voltage | VDD2 - 0.1 V min; IO = -200 µA |
| Logic Output Low Voltage | 0.4 V max; IO = +200 µA |
| VDD1 Supply Range | 4.5 V to 5.25 V; isolated-side supply |
| VDD2 Supply Range | 3 V to 5.5 V; nonisolated-side serial I/O supply |
| IDD1 Supply Current | 12 mA max; VDD1 = 5.25 V |
| IDD2 Supply Current | 8 mA max at VDD2 = 5.5 V; 4 mA max at VDD2 = 3.3 V |
| Master Clock Input Frequency | 5 MHz min, 20 MHz max; timing specification fMCLKIN |
| Data Access Time | 25 ns max; after MCLK rising edge |
| Data Hold Time | 15 ns min; after MCLK rising edge |
| Input-to-Output Momentary Withstand Voltage | 5000 V rms min; 1-minute duration |
| Minimum External Clearance | 7.8 mm min; input terminals to output terminals, shortest distance through air |
| Minimum External Creepage | 7.8 mm min; input terminals to output terminals, shortest path along body |
| Operating Temperature Range | -40°C to +105°C; Y version/orderable AD7401YRWZ-REEL7 |
| Datasheet Source | Analog Devices AD7401 Rev. F manufacturer technical datasheet |
| Datasheet Status | request_only |
Product Overview
AD7401YRWZ-REEL7 is a Signal_Chain device described by the extracted datasheet facts as an isolated sigma-delta modulator. The supplied product record names Texas Instruments as manufacturer, but the datasheet and ordering guide identify the AD7401 as an Analog Devices device, so this manufacturer conflict should be retained in sourcing records.
The converter uses a second-order sigma-delta modulator and outputs a high speed 1-bit data stream. Its master clock input supports 5 MHz to 20 MHz operation, with 25 ns maximum data access time after the MCLK rising edge and 15 ns minimum data hold time. The filtered output is truncated to at least 16 bits, and differential nonlinearity guarantees no missing codes to 16 bits.
Analog-side performance is specified around a ±200 mV input range, with an absolute full-scale range of ±320 mV. Dynamic specifications include 80 dB minimum SNR, 82 dB typical SNR, 11.5 effective number of bits, and -92 dB typical THD. The RW-16 wide-body SOIC package provides 7.8 mm minimum external clearance and creepage, supporting isolated analog measurement and serial data acquisition designs.
Key Features
- Second-order sigma-delta modulator architecture
- High speed 1-bit density-of-ones serial output
- 5 MHz to 20 MHz master clock input
- 16-bit minimum filtered output resolution
- No missing codes guaranteed to 16 bits
- ±200 mV specified analog input range
- ±320 mV full-scale analog input range
- 5000 V rms input-to-output momentary withstand voltage
- 7.8 mm minimum external clearance and creepage
- -40°C to +105°C operating temperature range
Typical Applications
- Isolated analog signal acquisition
- Isolated current measurement interfaces
- Sigma-delta data acquisition chains
- Serial 1-bit converter outputs
- Wide-body SOIC isolation layouts
- Mixed-voltage serial I/O systems
Procurement Notes
When requesting a quote for AD7401YRWZ-REEL7, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.
If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.
For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.
FAQ
What type of converter is AD7401YRWZ-REEL7?
The extracted datasheet facts identify AD7401YRWZ-REEL7 as an isolated sigma-delta modulator using a second-order sigma-delta architecture. Its analog input is converted into a high speed 1-bit density-of-ones serial data stream.
What clock range does AD7401YRWZ-REEL7 support?
The master clock input frequency is specified from 5 MHz minimum to 20 MHz maximum. The extracted timing facts also list 25 ns maximum data access time and 15 ns minimum data hold time after the MCLK rising edge.
What analog input range is specified for this part?
Specified analog input performance is listed for a ±200 mV range with VIN− at 0 V in the specification table. The extracted facts also identify ±320 mV as the absolute full-scale analog input range.
What package is used for AD7401YRWZ-REEL7?
The package is a 16-lead SOIC_W wide-body RW-16 option with a 10.10 mm to 10.50 mm by 7.40 mm to 7.60 mm body and 1.27 mm pitch.
Is there a manufacturer conflict in the extracted facts?
Yes. The supplied product information lists Texas Instruments, but the extracted datasheet fact states that the datasheet and ordering guide identify AD7401 as an Analog Devices device. This conflict should be considered during sourcing review.
Technical Review & Sourcing Note
Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: August 17, 2026.
This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.