AD7402-8BRIZ-RL Isolated Sigma-Delta Modulator

Analog Devices Signal_Chain — specifications, applications, sourcing support and RFQ.

AD7402-8BRIZ-RL Isolated Sigma-Delta Modulator

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Part Number
AD7402-8BRIZ-RL
Manufacturer
Analog Devices
Package
8-lead wide-body SOIC, increased creepage
Category
Signal Chain
Product Type
Operational Amplifier

Quick Sourcing Note

AD7402-8BRIZ-RL from Analog Devices is a Signal_Chain isolated sigma-delta modulator supplied in an 8-lead wide-body SOIC package with increased creepage. The device provides a 16-bit truncated filter output, a 10 MHz internal clock, and a nominal ±250 mV differential input signal range with a -320 mV to +320 mV full-scale analog input range. It supports VDD1 from 4.5 V to 5.5 V and VDD2 from 3 V to 5.5 V across -40°C to +105°C operation. Key isolation parameters include 5000 Vrms momentary withstand voltage, 8.1 mm clearance and creepage, and 1250 Vpeak maximum working insulation voltage for isolated signal-chain measurement designs.

Specifications

TypeDescription
Part NumberAD7402-8BRIZ-RL
ManufacturerAnalog Devices
Product TypeOperational Amplifier
CategorySignal Chain
Package / Case8-lead wide-body SOIC, increased creepage
Component TypeOther
Resolution16 bits; filter output truncated to 16 bits
Internal Clock Rate10 MHz; internal clock
Integral Nonlinearitytyp ±1 LSB, max ±5 LSB; VDD1=4.5-5.5 V, VDD2=3-5.5 V, VIN+=-250 mV to +250 mV, VIN-=0 V, TA=-40°C to +105°C, sinc3 filter, 256 decimation rate
Differential Nonlinearitytyp ±0.99 LSB; guaranteed no missed codes to 16 bits
Offset Errortyp ±0.2 mV, max ±0.75 mV; static performance
Offset Drift vs Temperaturetyp 1.7 µV/°C, max 5 µV/°C; TA=-40°C to +105°C
Offset Drift vs VDD1typ 85 µV/V; VDD1 variation
Gain Errortyp 0.2 %FSR, max ±0.5 %FSR; static performance
Gain Error Drift vs Temperaturetyp 18 ppm/°C, max 32 ppm/°C; TA=-40°C to +105°C
Gain Error Drift vs Temperaturetyp 11 µV/°C, max 20 µV/°C; TA=-40°C to +105°C
Gain Error Drift vs VDD1typ 0.2 mV/V; VDD1 variation
Analog Input Voltage Rangemin -320 mV, max +320 mV; full-scale analog input range
Nominal Differential Input Signal Range±250 mV; general description operating input signal
Input Common-Mode Voltage Range-200 mV to +300 mV; analog input
Dynamic Input Currenttyp ±19 µA, max ±28 µA; VIN+=±250 mV, VIN-=0 V
Dynamic Input Currenttyp 0.05 µA; VIN+=0 V, VIN-=0 V
Input Capacitancetyp 14 pF; analog input
Signal-to-Noise and Distortion Ratiomin 74 dB, typ 82 dB; VIN+=35 Hz
Signal-to-Noise Ratiomin 86 dB, typ 87 dB; VIN+=35 Hz; 39 kSPS reconstruction with appropriate digital filter noted in description
Total Harmonic Distortiontyp -84 dB; VIN+=35 Hz
Spurious-Free Dynamic Rangetyp -84 dB; peak harmonic or spurious noise, VIN+=35 Hz
Effective Number of Bitsmin 12 bits, typ 13.5 bits; VIN+=35 Hz
Noise Free Code Resolutiontyp 14 bits; dynamic specifications
Isolation Transient Immunitymin 25 kV/µs, typ 30 kV/µs; isolation transient immunity
Output High Voltagemin VDD2 - 0.1 V; IO=-200 µA
Output Low Voltagemax 0.4 V; IO=+200 µA
VDD1 Supply Voltagemin 4.5 V, max 5.5 V; power requirements
VDD2 Supply Voltagemin 3 V, max 5.5 V; power requirements
VDD1 Supply Currenttyp 26 mA, max 31 mA; VDD1=5.5 V
VDD2 Supply Currenttyp 6 mA, max 7 mA; VDD2=5.5 V
VDD2 Supply Currenttyp 4.5 mA, max 5.5 mA; VDD2=3.3 V
Power Dissipationtyp 209 mW; VDD1=VDD2=5.5 V
Master Clock Output Frequencymin 9.4 MHz, typ 10 MHz, max 10.6 MHz; VDD1=4.5-5.5 V, VDD2=3-5.5 V, TA=-40°C to +105°C
Master Clock Mark Space Ratio45/55 to 55/45; clock output
Data Access Time After MCLKOUT Rising Edgemax ±10 ns; measured with ±200 µA load and 25 pF load capacitance
Data Hold Time After MCLKOUT Falling Edgemax 44 ns; measured with ±200 µA load and 25 pF load capacitance
Master Clock Low Timemin 33 ns; timing specifications
Master Clock High Timemin 33 ns; timing specifications
Input-to-Output Resistancetyp 10^12 Ω; device considered 2-terminal; pins 1-4 shorted and pins 5-8 shorted
Input-to-Output Capacitancetyp 2.2 pF; f=1 MHz; device considered 2-terminal
Junction-to-Ambient Thermal Resistancetyp 105 °C/W; thermocouple at center of package underside, 4-layer board with thin traces
Input-to-Output Momentary Withstand Voltagemin 5000 Vrms; 1-minute duration
Minimum External Air Gap Clearancemin 8.1 mm; measured input terminals to output terminals, shortest distance through air
Minimum External Tracking Creepagemin 8.1 mm; measured input terminals to output terminals, shortest distance along body
Minimum Internal Clearancemin 0.034 mm; insulation distance through insulation
Comparative Tracking Index>400 V; DIN IEC 112/VDE 0303 Part 1
Isolation GroupGroup II; Material Group per DIN VDE 0110, 1/89, Table I
UL Isolation Voltage5000 Vrms; UL 1577 Component Recognition, single protection
CSA Basic Insulation Working Voltage810 Vrms (1145 Vpeak) maximum; CSA 60950-1-07 and IEC 60950-1, pollution degree 2, Material Group III
CSA Reinforced Insulation Working Voltage405 Vrms (583 Vpeak) maximum; CSA 60950-1-07 and IEC 60950-1, pollution degree 2, Material Group III
IEC 60601-1 Reinforced Insulation Working Voltage250 Vrms (353 Vpeak) maximum; reinforced insulation per IEC 60601-1
VDE Reinforced Insulation Working Voltage1250 Vpeak; DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
UL File NumberE214100; UL recognition
CSA File Number205078; CSA approval
VDE File Number2471900-4880-0001; VDE certification
UL Production Proof Test Voltage>=6000 Vrms for 1 second; current leakage detection limit=15 µA
VDE Production Proof Test Voltage>=2344 Vpeak for 1 second; partial discharge detection limit=5 pC
Installation ClassificationI to IV; rated mains voltage <=300 Vrms
Installation ClassificationI to IV; rated mains voltage <=450 Vrms
Installation ClassificationI to IV; rated mains voltage <=600 Vrms
Installation ClassificationI to IV; rated mains voltage <=1000 Vrms
Climatic Classification40/105/21; DIN V VDE V 0884-10 insulation characteristics
Pollution Degree2; DIN VDE 0110, Table 1
Maximum Working Insulation Voltage1250 Vpeak; VDE V 0884-10 insulation characteristics
Input-to-Output Test Voltage Method B12344 Vpeak; VIORM x 1.875 = VPR, 100% production test, tm=1 second, partial discharge <5 pC
Input-to-Output Test Voltage Method A After Environmental Test Subgroup 12000 Vpeak; VIORM x 1.6 = VPR, tm=60 seconds, partial discharge <5 pC
Input-to-Output Test Voltage Method A After Safety Test Subgroup 2 or 31500 Vpeak; VIORM x 1.2 = VPR, tm=60 seconds, partial discharge <5 pC
Highest Allowable Overvoltage8000 Vpeak; transient overvoltage, tTR=10 seconds
Surge Isolation Voltage12000 Vpeak; 1.2 µs rise time, 50 µs 50% fall time
Safety Limiting Case Temperature150°C; maximum allowed in event of failure
Safety Limiting Power Dissipation1.19 W; Side 1 PVDD1 and Side 2 PVDD2 power dissipation, maximum allowed in event of failure
Insulation Resistance>10^9 Ω; at TS, VIO=500 V
Absolute Maximum VDD1 to GND1-0.3 V to +6.5 V; TA=25°C unless otherwise noted
Absolute Maximum VDD2 to GND2-0.3 V to +6.5 V; TA=25°C unless otherwise noted
Absolute Maximum Analog Input Voltage to GND1-1 V to VDD1 + 0.3 V; TA=25°C unless otherwise noted
Absolute Maximum Output Voltage to GND2-0.3 V to VDD2 + 0.3 V; TA=25°C unless otherwise noted
Absolute Maximum Input Current±10 mA; any pin except supplies; transient currents up to 100 mA do not cause SCR latch-up
Operating Temperature Range-40°C to +105°C; absolute maximum ratings and product operating range
Storage Temperature Range-65°C to +150°C; absolute maximum ratings
Junction Temperature150°C; absolute maximum ratings
Pb-Free Reflow Soldering Temperature260°C; absolute maximum ratings
ESD Rating2 kV; absolute maximum ratings
FICDM ESD Rating±1250 V; JESD22-C101; RC network 1 Ω, package capacitance, Class IV
HBM ESD Rating±4000 V; ESDA/JEDEC JS-001-2011; RC network 1.5 kΩ, 100 pF, Class 3A
Maximum Continuous Working Voltage AC Bipolar1250 Vpeak; 20-year minimum lifetime, VDE approved working voltage
Maximum Continuous Working Voltage AC Unipolar1250 Vpeak; 20-year minimum lifetime
Maximum Continuous Working Voltage DC1250 Vpeak; 20-year minimum lifetime
Datasheet Statusrequest_only

Product Overview

AD7402-8BRIZ-RL is an Analog Devices isolated sigma-delta modulator for Signal_Chain applications requiring a low-level differential analog input across an isolation barrier. Its nominal differential input signal range is ±250 mV, with a full-scale analog input range from -320 mV to +320 mV and an input common-mode range from -200 mV to +300 mV.

The device uses a 10 MHz internal clock and provides a master clock output specified from 9.4 MHz to 10.6 MHz. With the filter output truncated to 16 bits, static performance includes typical ±1 LSB integral nonlinearity, typical ±0.99 LSB differential nonlinearity with no missed codes to 16 bits, and typical ±0.2 mV offset error.

The package is an 8-lead wide-body SOIC with increased creepage. Isolation-related parameters include 5000 Vrms input-to-output momentary withstand voltage for 1 minute, 8.1 mm minimum external clearance and creepage, 25 kV/µs minimum isolation transient immunity, and 1250 Vpeak maximum working insulation voltage. Operating temperature range is -40°C to +105°C, with Pb-free reflow soldering temperature specified at 260°C.

Key Features

  • 16-bit filter output from isolated sigma-delta modulation
  • 10 MHz internal clock with specified MCLKOUT frequency range
  • Nominal ±250 mV differential input signal range
  • -320 mV to +320 mV full-scale analog input range
  • 5000 Vrms input-to-output momentary withstand voltage
  • 8.1 mm minimum external clearance and creepage
  • 25 kV/µs minimum isolation transient immunity
  • VDD1 4.5 V to 5.5 V, VDD2 3 V to 5.5 V
  • -40°C to +105°C operating temperature range
  • 1250 Vpeak maximum working insulation voltage

Typical Applications

  • Isolated differential signal measurement
  • Signal-chain isolation interfaces
  • Sigma-delta reconstruction filtering
  • High-voltage barrier monitoring
  • Low-level analog input conversion
  • Isolated data output designs

Procurement Notes

When requesting a quote for AD7402-8BRIZ-RL, buyers should confirm the manufacturer, package or case, required quantity, target date code, compliance documents, packing method, destination country and expected delivery schedule.

If alternatives are acceptable, buyers should share the approved vendor list, required electrical or optical limits, package constraints and qualification requirements. Any alternative part should be reviewed by the buyer's engineering team before production use.

For analog and signal-chain sourcing, supply voltage, bandwidth, accuracy, noise level, package, temperature grade, input/output configuration and qualification requirements should be verified before approval.

FAQ

What type of device is AD7402-8BRIZ-RL?

AD7402-8BRIZ-RL is an Analog Devices isolated sigma-delta modulator in the Signal_Chain category. The extracted datasheet facts identify a 16-bit truncated filter output, 10 MHz internal clock, and an 8-lead wide-body SOIC package with increased creepage.

What input range does AD7402-8BRIZ-RL support?

The nominal differential input signal range is ±250 mV. The full-scale analog input voltage range is specified from -320 mV to +320 mV, and the analog input common-mode voltage range is -200 mV to +300 mV.

What are the main supply voltage requirements?

The VDD1 supply voltage range is 4.5 V to 5.5 V, while VDD2 operates from 3 V to 5.5 V. Supply current is specified at 26 mA typical for VDD1 at 5.5 V and 6 mA typical for VDD2 at 5.5 V.

What isolation ratings are specified for this modulator?

The device has a 5000 Vrms input-to-output momentary withstand voltage for 1 minute, 8.1 mm minimum external clearance and creepage, 25 kV/µs minimum isolation transient immunity, and 1250 Vpeak maximum working insulation voltage.

Technical Review & Sourcing Note

Prepared by LDeepAI Component Sourcing Team. Reviewed for RFQ, documentation and alternative sourcing use. Last updated: August 17, 2026.

This page is based on manufacturer datasheet information and LDeepAI sourcing review. Specifications should be verified against the official manufacturer datasheet before final procurement or design approval. Final electrical, optical and reliability approval should be confirmed by the buyer's engineering team.

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